[context is SERDES inputs to FPGA] > Also, one has to count the number of 0->1 transitions in each word, such > that the event counter can be accumulated with the contribution from each > word.
That gets complicated. My straw man would be to get a single transition per word working first. Let's check the numbers. If the serial bit rate is 3.2 gigabits, that's 100 MHz per 32 bit word. If you are limited to 1 rising edge per word, that limits your counting to 100 MHz. If you are interest in ADEV of a 10 MHz source, 100 MHz is a fine limit. Below, I'm assuming "transition" means rising edge. So my first proposal for an API between the front end and the back end would be: 5 bits of offset for the transition 1 bit for "Yes, there was a transition" 1 bit for error (More than one transition) Plan two would be something like: 5 bits of offset for last transition. n bits for number of transitions (with 0 for none, and xx for too many, aka error) -- These are my opinions, not necessarily my employer's. I hate spam. _______________________________________________ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.