Perry Sandeen wrote:
List,
Wrote: However the exercise is probably pointless as the frequency difference
between the 2 signals as seen at the output of the cascaded divide and mix
chains are reduced by this scheme.
Umm. I guess I didn’t express my thoughts effectively enough.
The idea is to subtract 9 MHz in each DBM then take the 1 MHz error signal and
use it to phase lock the next PLL at 10 MHz. Thus the error is multiplied by
10 in each section. So after four sections the error is multiplied by a factor
of 10,000.
No, the error is actually divided by 10,000.
The method you describe is used in narrow range offset sources to reduce
the noise contribution of the tunable source.
What I forgot to mention in my original post is the use of a decade counter
(1/2 of a 74HC390) from the output of each PLL to one input of its phase
detector so it would lock on the 1 MHz signal from the previous stage. Maybe
this is what caused confusion, If so, I apologize. If I’ve still missed
something please correct me.
Using a 74HC390 to divide by 10 is a bad idea because of the ripple
carry between sections.
Either resynchronise the output or use a fully synchronous divide by 10
like a Johnson counter.
This math is the same as multiplying 10 MHz to 10 GHz. What this method avoids
is using very tricky-to-use frequencies. And I suspect much cheaper.
No it isnt.
Your technique reduces the noise contribution from the DUT by a factor
of 10 for each stage.
Wrote:< You can see the Tracor frequency error meter, used the same mixer
method you describe but using 9 and 10 MHz frequency to mix together and a decade
frequency multiplier. The limit of the system is the phase noise of the system and
sources. The Tracor use an optional Xtal filter to limit the noise. The filter can
be inserted for high multiplication rate or for noisy oscillators.
< See tracor schematic
ttp://www.ko4bb.com/Manuals/09)_Misc_Test_Equipment/Tracor_527E.pdf
Thanks. I knew my method wasn’t original, I was trying just update it and make
it both simpler and cheaper with newer chips
Wrote:<You need to multiply the input signals to a nominal 100 MHz then
subtract 90 MHz using a mixer and repeat the process.
This may be true but I don’t understand why. I think my math process is the
same as yours. I may need more “Edjurcation”.
If the DUT has a frequency of 10MHz +delta the output of the first stage
is 10MHz + delta/10.
This divides the error by ten with every stage- not very useful at all
for this application.
Multiplying the error either using a harmonic or a PLL multiplier is
necessary.
Wrote: The normal term for a gizmo that multiplies and then mixes down is an
error multiplier.
A. Right
Also thanks to Urlich who sent me a PDF copy of the Quartzlock (UK) Limited ON
IMPROVED METHOD OF RESOLVING THE FREQUENCY DIFFERENCE BETWEEN TWO VERY ACCURATE
AND STABLE FREQUENCY SIGNALS.
Wrote:< Using the CD4046 (or HC4046) as the phase locked oscillator would
probably be counterproductive as its phase noise is very high (its in effect an RC
oscillator with an effective Q of around1/4)
A. I don’t know. Maybe there is a better IC choice for the PLL. I guess
building one would prove its feasibility.
An additional thought came to me that might make the whole process easier.
ASS-U_ME we have a “gold standard” 10 MHz signal from a GPS, Rb, or cesium
beam. We input it into our frequency counter’s external reference input.
We take the to-be-measured 10 MHz source and put it into the external input of
a synthesized signal generator. Set the signal generator frequency output to
100 Mhz or 200 Mhz or whatever are your highest limits are of the
generator/counter setup and count the difference using and extended start and
stop signal for the counter.
If one has a HP 3336A/B (referenced to our “standard”) it can give up to a 1
micro-Hz clock signal. Or one can chain together a bunch of 74HC390 decade
counters.
Forget a chain of 74HC390's the output is noisy due to the ripple carry
between sections.
Wrote:< DMTD is the obvious way to do this, but let's go the old fashion way
instead.
A. I don’t know what you mean by DMDT but am willing to try to learn.
A dual mixer time difference system uses a common offset oscillator with
a frequency a few Hz above or below that of the 2 oscillators being
compared.
This offset source is mixed with each DUT in separate mixers, the
outputs of which are low pass filtered.
One then compares the zero crossing times of the 2 outputs.
To reduce trigger noise a carefully designed zero crossing detector is
required.
With 10MHz inputs and a 1Hz offset the time difference between the 2 DUT
zero crossings is magnified by a factor of 10 million (1E7).
Thus a timing resolution of 10ns is equivalent to a 1fs phase resolution
at 10MHz.
The trick being to amplify the slope without adding excessive noise
before driving the inputs of a time interval counter or equivalent.
Wrote:< Going down, how low do you want to go? 100 KHz will give you 100X.
A. I thought when dividing down one was also dividing the error.
Using an offset oscillator and mixing down doesnt affect the phase error
(provided the offset oscillator is quieter than the DUT), however the
corresponding time interval is amplified.
Wrote:<Whatever way you do it, you are still stuck with the same old problem.
The input needs to be on a very specific frequency. With some designs it can be a
sub multiple of that frequency. With other designs it can be a multiple.
A. Not Necessarily. If one puts a DBM in each channel which is referenced to
a common oscillator. Granted one may need to add a post mixer filter. But this
is a diversion from the original issue.
Wrote:< Either way, 7.352 MHz is going to give you trouble. That's pretty much
why the error multiplier boxes all went into storage in the 1970's...
A. I have no idea what 7.352 MHz is or why it will cause trouble. Could you
please elaborate?
If you design an error multiplier for 10MHz inputs then using it at any
other frequency (such as 7.352MHz) requires a complete redesign using
different filters (and VCOs if you use PLL multipliers).
I blessed to have HP 5370’s, rubidium standards, a HP 3336B and GPS receivers
and don’t really need to fabricate any equipment. My reason for posting is to
come up with a relatively simple test equipment set-up that could be used by
those who have a more modest budget or live where the test equipment we in
North America can afford is unobtainiumly expensive.
Thanks to all who have commented as shared the actual results of their 10811
oscillators.
Regards,
Perrier
Bruce
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