On Fri, January 28, 2011 6:00 am, Luis Cupido wrote: > p.s.(what's cooking) > I need a relatively narrow tunning range > but absolutely free of close in spurs, > willing to see if a modest size DDS > (inside an FPGA) will do so... and what parameters will > be...
A couple of guys came up with a scheme a few years back for regenerating a clock to feed an ADC or DAC which used fractional-N techniques along with error spectrum shaping, such that the spurs were far enough away from the fundamental that a following analog PLL could be used to track the generated clock and reject the spurs. See section 3.3 - 4 in the following: http://www.tcelectronic.com/media/frandsen_travis_2006_clean_clocks_tc%281%29.pdf -- Chris Caudle _______________________________________________ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
