> Whilst the close in phase noise of the ADC used in the TSC5115 may be > comparable with that of a 74AC04 the phase noise floor of such ADCs is > degraded when clocked by a 74AC04... > In particular such ADCs have been be used to measure the jitter of > various logic families by using devices from the logic family to drive > the ADC clcok /encode inputs and comparing the increased noise floor > with that when the ADC clock/encode inputs are driven with a bandpass > filtered low phase noise sine wave.
The AC gate will definitely get noisier towards 100 MHz than at 10 MHz where I ran most of my measurements. It would be hard to measure the contribution of a 74AC gate at 10 MHz with one of these ADCs, but yes -- if you put it in the clock path it will degrade the performance of a ULN oscillator noticeably. It's worth keeping the Perseus's stock frequency reference in mind, though. The performance tests in the Analog app notes assume the use of an oscillator that costs >2x what the whole receiver does. So... will the output of an 80 MHz multiplier based on cascaded 74AC stages be noisier than the $10 80 MHz oscillator that came with the receiver? I'm guessing not. When I measured the 74AC04 at 100 MHz, its residual noise crossed the -150 dBc/Hz line between 1 and 3 kHz, so it probably would not degrade anything much noisier than a Sprinter-class OCXO. -- john, KE5FX _______________________________________________ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.