Jim Lux wrote:
On 6/20/11 9:46 AM, Luis Cupido wrote:
Gracias, Javier.
As you read in my previous email I'm basically
worried about close-in spurs (those that
will pass through the PLL loop filter).
will digest that 4th section... tks.
...
Since I'm inside an FPGA... I'm eager to get
spurs down without leaving the digital world...
Anyone knows any literature covering that ?
Tons..
Jouko Vankka wrote whole books about it.
Direct Digital Synthesizers and transmitters for software radio
Direct Digital Synthesizers: Theory, Design and Applications
You might want to look at various Error Feedback/Error Filtering
schemes which allow you to use a smaller cosine table and/or smaller
DAC and have better spur performance.
Vankka, J, "A direct digital synthesizer with a tunable error
feedback structure", IEEE Trans on Comm, V45, #4, pp416-420, 1997
Vankka's EF technique works quite well at suppressing spurs close to
the carrier (at the expense of pushing them farther out).
Reinhardt, V, "Spur Reduction Techniques in Direct Digital
Synthesizers", Proc Intl Freq Control Symp, 1993
Flanagan, M., Zimmerman, G., "Spur-reduced digital sinusoid synthesis"
IEEE Trans on Comm, V43, #7, pp2254-2262, 1995
(this one is about using dither to spread the spurs out)
O'Leary, P., Maloberti, F., "A direct-digital synthesizer with
improved spectral performance", IEEE Trans on Comm, V39, #7, 1991
You might also look at some of the spur cancellation things, such as
the one implemented in some of AD's DDS parts.. Basically, it's a
second NCO that generates a coherent signal that is subtracted/added
to the primary signal to "notch" out the spur.
See also:
http://www.iro.umontreal.ca/~mignotte/IFT3205/Documents/TipsAndTricks/UltraLowPhaseNoiseDSPOscillator.pdf
<http://www.iro.umontreal.ca/%7Emignotte/IFT3205/Documents/TipsAndTricks/UltraLowPhaseNoiseDSPOscillator.pdf>
Bruce
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