On 07/21/2011 07:10 PM, dk...@arcor.de wrote:
IMHO, that would require a sine table with a steerable number of entries. Very problematic for a tunable DDS, but doable for a fixed frequency application, although address mirroring for ROM size reduction would require real address comparators instead just using the 2 MSBs as a selector. The table could also be in RAM instead of ROM without large increase of the cost in an FPGA, so with some processor support one might approach "tunable".
True, this is an issue if you waveshape to sine/cosine or other suitable waveform.
The scaling error is N/2^n so you would have to multiply by 2^n/N to get proper scale. A few shifted down adds to form a multiply approximation would help to reduce the phase-jump with associated spurious generation.
However, in Luis application he only uses the MSB. The MSB would get a PWM factor skewed from 50%, in fact it becomes N/2^n. Again, PWM factor can be adjusted with the addition/multiplication trick mentioned above... if it is important for the application. Otherwise it is just wasted logic.
Cheers, Magnus _______________________________________________ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
