I think this is the simplest design that can still work, just one flip flop, divider and a capacitor.
What level of performance did you get? I think it depends on how big the integrating capacitor is and how stable the VCXO is. I guess if you switched to using the t-bolt the performance was not as good as a t-bolt. On Sat, Dec 31, 2011 at 10:23 AM, WarrenS <warrensjmail-...@yahoo.com>wrote: > Chris > > Here is a GPSDO I built that better fits Your definition of "Simple". I > used this as my freq standard before getting a TBolt. > > 1) Feed the PPS output of an oncore GPS timing engine which has 1 Hz or > better yet 100 Hz output to the clk of a D FlipFlop (74HC74) > > 2) Feed the FF's D from a 10 MHz osc which has been divided down to 100KHz > or less using 74HC390. > The FF output shows if the Phase of the Osc is greater or less than the > GPS signal and the FF will toggle back and forth when the phases are near > equal due to the typical 40 ns jitter on the GPS pulse signal. > > 3) Add a RC filter to the FF output using a big cap, so the voltage out of > the RC filter is 0 to 5 volts depending on the duty cycle of the FF. > (A small R in series with the cap will help stabilize it if a real Big cap > is used). > > 4) Feed the filtered analog FF output voltage (No buffering necessary) to > the EFC of an 10 MHz osc that has its EFC input desensitized with a couple > of Rs and has been set to be real near 10 MHz at the nominal analog FF's > 2.5 volts output using the Osc's mechanical tuning and/or add a fine freq > adj pot....... Chris Albertson Redondo Beach, California _______________________________________________ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
