On 1/16/12 2:44 AM, Attila Kinali wrote:
On Sun, 15 Jan 2012 11:27:27 -0500
paul swed<paulsw...@gmail.com> wrote:
FPGAs are generally intended for the mass market with a steep learning
curve. Though they can be pressed into whats of interest to time-nuts it
simply seems like a overly complicated technology and method for a non-mass
market solution.
Actually, they are not. In the mass market, you dont want to use FPGAs
due to their high cost. As soon as you produce more then 10k pieces (in total)
you start thinking about doing an ASIC.
And the learning curve isn't any more steep than for learning how to
work with a uC. It's just that most people know already a bit of programming
which makes it far easier to learn enough C to do something with a uC.
At the same time, programming experience makes it more difficult to
learn VHDL/Verilog, because people think it works like a programming language
which it definitly does not.
But yes, you are right. An FPGA is probably not the right thing. Not because
it is more difficult, but rather because there are less tools and less
documentation available. Hence making it more difficult for the hobbyist
to handle FPGAs than uCs.
Precisely so, particularly the tools. FPGAs (especially bigger ones,
not just PALs and CPLDs) have been around about 20-25 years. I seem to
remember going to some Xilinx seminars in the late 80s, when they were
proud of their simulated annealing place and route running on a 286.
So they've had only a few decades of development on the tool chain,
compared to more traditional high level languages, where the basic
computer architecture has been around 100 years, and compilers have been
around for 60. There's also more "genericness" by now in the VonNeumann
Model programming world: there must be 100 different CPU families out
there, and we've converged to only a few basic programming models.
THere's only a few FPGA architectures out there, and there's really only
two different languages Verilog and VHDL.
And as Attila points out, both of those look superficially like ordinary
programming (particularly VHDL) and you can even write "sequential
programs" in them, but the underlying hardware isn't even remotely like
that, so you are seduced into a very non-optimal design style.
_______________________________________________
time-nuts mailing list -- time-nuts@febo.com
To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts
and follow the instructions there.
