On Mon, 30 Apr 2012 06:51:37 +1200, Bruce Griffiths <bruce.griffi...@xtra.co.nz> wrote:
>The circuit for the Tek 2440 is in the manual. >However, it isnt that well executed. I like using the 2440 as an example because the design and theory are readily available online. Its execution only had to be good enough for 40ps equivalent time sampling and less than 50 measurements per second. Unfortunately the self calibration logic is obfuscated inside of a Tektronix black box custom ASIC. >Relying on the overload recovery of an unclamped jfet input opamp limits >the recovery time and performance as does the unisolated input >capacitance of the opamps used to control the current source transistor >emitter currents, the Wavecrest interpolators which incorporate several >refinements to improve the transient response of the current sources are >far better in this respect. By unclamped JFET input opamps do you mean U590B and U590C which are used to adjust the ramp start to zero volts and operate open loop during the measurement? With such a slow measurement rate, that feedback loop has at least 20ms to complete settling. I notice that they attenuated the open loop gain by a factor of 6. I wonder if that was to lower the noise or to add phase margin to the control loop. >The Wavecrest interpolators also have sub picosecond resolution although >their noise is around 3-6ps. Is there a published schematic and theory for the Wavecrest other than the patent? The best information I have found through Google is from your own posts here. > >Bruce > >paul swed wrote: >> Do you have an actual circuit? >> It looks a lot like the old hp5360 counter interpolator. >> Regards >> Paul >> >> On Sun, Apr 29, 2012 at 3:51 AM, Bruce Griffiths<bruce.griffi...@xtra.co.nz >> >>> wrote: >>> >> >>> The essentials of a Wikinson TDC can be simplified to the attached circuit >>> which only requires the addition of a zero crossing comparator to monitor >>> the voltage across the capacitor C1. >>> >>> A few refinements to improve the capacitor charging current switching >>> transitions and the addition of an upper voltage clamp together with the >>> use of faster transistors may be useful. >>> >>> Apart from level shifting to drive the npn and pnp longtailed pairs only a >>> 2 bit shift register is required for the synchronisers reducing the number >>> of external (to an FPGA or CPLD) logic packages required. >>> The jitter of the count logic etc., isn't critical and can be implemented >>> in an FPGA or CPLD. >>> >>> With a 100MHz synchroniser and counter clock a resolution of 10ps can be >>> achieved with a 1000:1 ratio between charge and discharge currents. _______________________________________________ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
