> > The clock-correction seemed a bit crude. I expected to find a PI-filter > and a phase-accumulator to steer the 300 MHz to 37 MHz synthesis.
Actually I do use a phase accumulator, in Fig. 26 it's inside the "binary search" block. The phase is accumulated during several seconds (longer for a noisy signal), then the binary search takes a decision in which direction to modify the clock correction. A standard binary search cannot recover from a wrong decision, therefore I use smaller steps which slowly converges to the final value. I assume that the clock correction could also be implemented with a classical PLL algorithm, it would be interesting to compare the performance. _______________________________________________ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
