What if I post a schematic with a Lattice M4-64/32 CPLD? If you can program this CPLD I can send the .JED file, the schematic...
On Fri, Jul 6, 2012 at 7:07 PM, Bill Dailey <docdai...@gmail.com> wrote: > Yes, that i know. Just don't have the wherewithal to implement that > myself. > > ---------------- > The integer greatest common divisor 10MHz/25.576MHz is 16KHz so a simple > PLL should go through that frequency. > > Sent from my iPhone > > _______________________________________________ > time-nuts mailing list -- time-nuts@febo.com > To unsubscribe, go to > https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts > and follow the instructions there. > _______________________________________________ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.