Good: I'll modify my VHDL to include this. The last will be the 50% duty cycle divide-by-3 so that a 48KHz or 96KHz will be available.
On Sat, Jul 7, 2012 at 3:47 PM, Magnus Danielson <mag...@rubidium.dyndns.org > wrote: > On 07/07/2012 03:10 PM, John Ackermann N8UR wrote: > >> Hi Don -- >> >> The problem with the Clock-Block is that it can't generate exactly the >> correct frequency in this case -- the closest it can get is several PPM >> off. And, I'm not sure the phase noise/jitter from the Clock-Block is >> good enough. >> >> I don't know whether you could program a PIC to generate a precise >> wordclock; the maximum output frequency you can get from either TADD-2 >> device is about 800 kHz, so it couldn't generate a 12 or 24 MHz >> oscillator replacement frequency. >> > > You can get pretty good 24,576 MHz TCXOs from CMAC with EFC input. One of > those and a pair of dividers (to 16 kHz) and a fairly simple PI-loop PLL (2 > resistors, 1 cap and an op-amp will suffice) should get you started. > Getting the 48 kHz or 96 kHz out of the feedback divider comes for free if > you realize that you should put the divide by 3 last in the chain, as the > sequence of divide by two dividers will remain. Typical for a small CPLD or > a standard PLL chip. > > Cheers, > Magnus > > > _______________________________________________ > time-nuts mailing list -- time-nuts@febo.com > To unsubscribe, go to > https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts > and follow the instructions there. > _______________________________________________ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
