Hi The nice thing about going into the LVDS inputs is that you are differential right at the FPGA. Often that's where a *lot* of junk is running around.
Bob -----Original Message----- From: time-nuts-boun...@febo.com [mailto:time-nuts-boun...@febo.com] On Behalf Of ct1dmk Sent: Monday, July 23, 2012 8:37 AM To: Discussion of precise time and frequency measurement Subject: Re: [time-nuts] Zero-Crossing Detector Design? Hi Bob, No, never tried but it looks a good idea. Our boards all have 5v so there was never any pressure... ... for a 0.5v in the tail resistor to vcc and 0.7v of vbe I could easily allow collectors to swing some 300mv around 1.2V... a couple of resistors more than my single ended solution... but it should work fine from 3v3. Must try that. tks, lc ct1dmk, On 7/23/2012 12:35 PM, Bob Camp wrote: > Hi > > Did you try running it at 3.3V and going into an LVDS input on the FPGA? > > Bob > > -----Original Message----- > From: time-nuts-boun...@febo.com [mailto:time-nuts-boun...@febo.com] On > Behalf Of ct1dmk > Sent: Monday, July 23, 2012 7:26 AM > To: Discussion of precise time and frequency measurement > Subject: Re: [time-nuts] Zero-Crossing Detector Design? > > For the specific application of driving an FPGA clock pin (that has an > enormous input bandwidth) many things can go wrong. > All fine about the advantages and disadvantages of > the gate with resistor feedback, all I can say is that over here I it > was not the best solution > we found over many FPGA board versions with external clock. > The latest design and the one we keep using standard now, uses a > differential pair of PNP > transistors (BFT91), this will have a moderate gain of x10 or so and the > resistors set > for making a limited wave of 0 to 3.0V (simple change of resistors can > make it 0-2.0V > or else required). we use a 100MHz narrow band limited bandwidth sin > signal so no filter > added, but we could add if we need one. > The output signal into the FPGA looks very clean and has a few ns rise > and fall times > (not super steep, but the fpga input does the rest. It does depend also > on the resistor values and current used in the transistor pair). > This was the way we could get the very minimum clock jitter in the FPGA > and a > simple circuit quite tolerant to input levels and make a very clean and > well defined signal > into the FPGA. Way better than 74F or 74LV gates etc. > The only inconvenience is that it needs +5V for the circuit to work (the > VCCIO of +3.3V is not enough). > > My 2 euro cents ;-) > > Luis Cupido > ct1dmk. > > > On 7/22/2012 9:32 PM, Bill Fuqua wrote: >> Wow, I have not checked this list for some time. But there is a lot said >> about zero crossing detectors. >> Lots and lots of replies, so many that I have not looked at all of them. >> 1. Do not use CMOS inverters. Even though so much has been published on >> using these in linear mode by >> adding a feedback resistor, they can be a nightmare. The fast ones >> (74HC, 74AC, etc) have so much high frequency gain they are >> likely to take off into oscillation on their own. >> 2. The first thing you can do to get a good clean zero crossing is to >> reduce the noise. This means to pass it >> thru a narrow band pass filter such as a crystal filter. The narrower >> this filter is the closer to a pure sinewave it becomes >> and the less noise you have. >> 3. In research when we want a precise trigger we use what is called a >> constant fraction discriminator. >> This may not be needed if you have a very clean signal and its amplitude >> does not vary and you are wanting to >> trigger exactly at zero. But a constant fraction discriminator triggers >> on a point that is a constant fraction of the >> amplitude of the signal. They require a delay so that a fraction of the >> peak of the cycle can be compared with the rising edge >> of that cycle. This is mostly used with triggering on pulses of varying >> heights and when subnanosecond >> timing is required. >> >> My suggestion is to clean up your signal as much as possible and reduce >> noise bandwidth using a bandpass filter and >> then use a low noise amplifier for the front end of your zero-crossing >> detector. >> >> 73 >> Bill wa4lav >> >> >> >> _______________________________________________ >> time-nuts mailing list -- time-nuts@febo.com >> To unsubscribe, go to >> https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts >> and follow the instructions there. >> > > _______________________________________________ > time-nuts mailing list -- time-nuts@febo.com > To unsubscribe, go to > https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts > and follow the instructions there. > > > _______________________________________________ > time-nuts mailing list -- time-nuts@febo.com > To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts > and follow the instructions there. > _______________________________________________ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. _______________________________________________ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.