On Mon, Sep 10, 2012 at 9:08 PM, Florian Teply <use...@teply.info> wrote:
> Apart from that, I'll also check with ACAM in Germany as they have > ready-made chips that would do that, and 65 to 120 ps RMS accuracy is > okay for the CMOS stuff. Maybe they sell their chips for only a few > hundred euros each... ;-) You might also want to have a look at this FMC with an ACAM chip on it: http://www.ohwr.org/projects/fmc-tdc/wiki It is made to work with this FMC carrier in PCIe format: http://www.ohwr.org/projects/spec/wiki The FMC carrier is a mature product. The TDC FMC is soon going to be commercialized. The design is open, so it could give you some ideas in any case. We have also played with a TDC core in the FPGA (http://www.ohwr.org/projects/tdc-core/wiki) using the same FMC carrier with a simple digital I/O mezzanine (http://www.ohwr.org/projects/fmc-dio-5chttla/wiki). This core is based on delay lines inside the FPGA, using logic elements. In your case it looks like a solution which would enable more channels in the FPGA at the cost of some accuracy would probably suit better. You can do this by e.g. sampling inputs with different phases of clocks in the 200 MHz realm, using the internal PLLs of FPGAs. Cheers, Javier _______________________________________________ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.