On 12/02/2012 01:29 AM, David wrote:
Originally the IBM PC design used an 8253 or 8254 PIT, programmable interval timer, located at ports 40h to 43h with Timer 0 clocked at 1.193182 MHz (1/3rd of 3.579545 MHz or 1/12th of 14.318 MHz) and set to divide by 65536 which generated about an 18.2 Hz interrupt rate on IRQ 0. Timer 1 generated the since deprecated DRAM refresh clock and Timer 2 goes to the PC speaker.
In a modern world, look for things like HPET and TSC: http://en.wikipedia.org/wiki/High_Precision_Event_Timer http://en.wikipedia.org/wiki/Time_Stamp_Counter You want to get a better reference clock to these timers. Cheers, Magnus _______________________________________________ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
