li...@rtty.us said: > That would be an input capture rather than an interrupt.
Thanks. Yes, that's the term I was trying to remember. li...@rtty.us said: > To be useful, you need an input capture that: > 1) Runs at a fast enough clock (1 GHz would be nice) > 2) Has enough bits to get to 1 pps (say 32 bits) > 3) Has a built in period set, so the hardware works without a lot of silly > stuff What do you mean by "period set"? (I did a bit of googling, but didn't hit anything close to pay dirt.) My expectation is that the counter/timer just counts on the local/CPU clock or some sub-multiple of that. When the external signal makes a low-to-high transition, the value in the counter is copied into a holding register and sets a status bit that may generate an interrupt. The counter just keeps counting through overflows and such. ---------- The enough-bits from [2] above can be partially implemented in software. When the counter overflows, it sets a status bit and maybe generates an interrupt. The software keeps the high bits in memory. When it sees that status bit, it bumps that counter. Getting everything right is not simple. There is a standard recipe for reading a hardware counter that lives in two registers. You read high, low, high. If the two high readings match, the answer is (either) high and low. If not, try again. Some hardware supports a hack to latch the high when you read the low. -- These are my opinions. I hate spam. _______________________________________________ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
