Hi The VCO is part of the process, the PLL and it's loop are another part. There's no reason why they can't put a good loop in a micro, other than chip area for the passive parts. What ever they do, the loop will probably be a compromise, since the frequencies involved are not known at design time. A 4 MHz reference and a 40 MHz reference will need different loop components running a 100 MHz VCO ….
Bob On Jan 1, 2013, at 3:45 PM, M. Simon <msimon6...@yahoo.com> wrote: > The NXP LPC111x series has a PLL that runs at 156 to 320 MHz. You then divide > the clock down (internally by 2,4,8, or 16) to what you want. 50 MHz is the > max. for the LPC111x series. Giving you capture ticks in 20nS increments. > > I have some experiments in the works with an LPC1114 chip and a 40 MHz > DSA222MAB TCVCXO clock (divided by 2 for the LPC1114 input). But those > experiments are just at the schematic stage. I do have the LPC1114s and the > DSA222MABs in hand. > > > Simon > > > Engineering is the art of making what you want from what you can get at a > profit. > _______________________________________________ > time-nuts mailing list -- time-nuts@febo.com > To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts > and follow the instructions there. _______________________________________________ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
