The response time to an external asynchronous interrupt is never deterministic. The external interrupt has to be synchronous with the uP clock to avoid the non deterministic synchronisation delay. Even when the external event is synchronous with the clock input to the uP and the uP uses a divider to produce its internal clock then there is the issue of divider phase shift. This phase shift can lead to sampling the waveform before the peak across the sampling cap. This is far from ideal, its better to sample at or slightly after the peak when the sensitivity to timing variations is far smaller. To complicate the issue further the time of occurrence of the peak is temperature dependent and the sampling switch on resistance is nonlinear so that peak delay varies with temperature and input signal amplitude.

Its generally quicker and cheaper to estimate the magnitude of such effects and make appropriate choices than just build a sequence of breadboards each of which then needs to be extensively characterised.

Bruce

Chris Albertson wrote:
You all are "inventing problem".  Solve them AFTER you find a problem you
can measure.   Interrupts are not an issue on a UP like the AVR because
they are completely deterministic.  It don't matter the lenth of time as
long as it is 100% deterministic and predictable.   On a multi-tasking OS
running on a super scaler CPU you have unknowable latentcy but this is not
the problem on a chip that does one machine cycle per clock cycle.


On Sat, Feb 15, 2014 at 6:50 PM, Brian Lloyd<br...@lloyd.com>  wrote:

On Sat, Feb 15, 2014 at 7:10 PM, Tom Van Baak<t...@leapsecond.com>  wrote:

For Arduino and other less fortunate uC you can always use external chips
to obtain optimal and jitter-free charge/discharge timing. I'm not that
familiar with Atmel chips; could capture/compare be used instead of
interrupts somehow?

One should investigate the Propeller.

--
Brian Lloyd, WB6RQN/J79BPL
706 Flightline Drive
Spring Branch, TX 78070
br...@lloyd.com
+1.916.877.5067
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