Wouldn't those types of problems tend to make the result worse in some obvious way, instead of better than expected? I'm getting an ADC swing from about .7V to about 2.4V; which corresponds to the usual diode sink at .7V and probably just blind luck with the 2.4V max being so close to the 2.5V VRef.
In the plot below, I zapped the DAC on my system to get a picture of the charge ramp. The red dots are the TIC with the 10ns uncorrected jitter from a nav receiver. The purple is a 30 second rolling average. Am I right in thinking this is a typical RC charge ramp? Not trying to be argumentative, I'm just trying hard to understand. http://www.evoria.net/AE6RV/TIC/ChargeRamp.png Bob >________________________________ > From: Bruce Griffiths <bruce.griffi...@xtra.co.nz> >To: Bob Stewart <b...@evoria.net>; Discussion of precise time and frequency >measurement <time-nuts@febo.com> >Sent: Monday, March 10, 2014 3:53 PM >Subject: Re: [time-nuts] Modeling vs reality question re my TIC > > >Metastability in the Flipflops? > >Charge injection when tristating tristate buffers? > >Neither of which are included in your models. > >Bruce > > _______________________________________________ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
