On 04/24/2014 10:41 AM, sg sg wrote:
Hi, I'm about to implement a PLL for a 24.576 MHz VCXO using the phase-frequency detector (PC2) of the NXP 74HCT9046A. From the datasheet (www.nxp.com/documents/data_sheet/74HCT9046A.pdf) it is not clear to me what the maximum operating frequency for this phase detector is--from the enable and disable times (page 20 and figure 19) I presume 24.576 MHz is too much. So I probably need to add dividers at the inputs. Can someone advise me on the choice of division ratio?
24,576 MHz is 128x192 kHz which makes essentially any divide by 2^N chip capable of the frequency a target. Is your reference signal also 24,576 MHz or some other frequency?
Cheers, Magnus _______________________________________________ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
