Mike not sure what the above means. As to the FPGA I suspect that may be a good approach i am messing with various micros and languages and they all sort of run out of steam especially when you need to be able to use numbers of instructions to make a DPLL. I did build a hardware counter that I could speed up slowdown or leave the same so that I could essentially build a phase accumulator. But not sure what patents are going to cause a problem. Regards Paul WB8TSL
On Fri, Aug 8, 2014 at 10:01 AM, Mike Harpe <m...@mikeharpe.com> wrote: > From my reading of the archives and research it appears that the design for > a BPSK WWVB receiver probably has a patent conflict. > > Isn't this a rehash of the old Heathkit patent on radio clocks that held > back their adoption for years? > > I have begun work on a BPSK receiver for WWVB using an FPGA. > > Someone should look into why the NIST did this at all since the receiver > design got a patent slapped on it right away. > > Mike Harpe, N4PLE > Sellersburg, IN > _______________________________________________ > time-nuts mailing list -- time-nuts@febo.com > To unsubscribe, go to > https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts > and follow the instructions there. > _______________________________________________ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
