Hi Mark, that really is up to you and your skill-set. I don't use FPGA's in products anymore because they are not field-serviceable generally, expensive, usually require some sort of recurrent registration of the compiler, the ones I like have external program storage so are not easily protected against theft, and are not needed if you have a good Microcontroller and a handful of discrete gates. I do use PLD's from time to time to do simple dividers etc. But integrating everything into an FPGA for a one-off if you are versed at programming them and know how to do IIR and FIR filters etc is a completely different story. Lastly, there is no need to generate a DC signal with a 1-bit DAC (sigma-delta, PWM etc) for a one-off design since there are very good and low-cost 12 bit or 16 bit DAC's available. I would use two cheap 12 bit DAC's (SPI or better I2C) cascaded to give me 20+ bits equivalent DAC resolution. Don't forget that the DAC reference is just as important as the DAC, maybe even more so for applications that will see larger temp variations. As I said before we have discussed this subject on numerous occasions over the last decade in very great detail, you may want to search and read through the archives - there is great detail on all of the above. Nowadays you can get a great 10MHz OCXO on Ebay for $10, buy a PLD/FPGA/Micro eval board for less than $30, and add a DAC and some low-pass filtering and voltage reference for probably less than $10. So you can do a complete, high-end double-oven GPSDO for around $50.. Adding the Crystek VCXO onto an Analog Devices PLL eval board would give you the desired high-frequency, low phase noise output. bye, Said In a message dated 9/29/2014 10:36:14 Pacific Daylight Time, hau...@keteu.org writes:
Said, would you suggest implementing the dividers and PFD in the FPGA, along with the digital filtering? Or feeding the FPGA with some version of the PFD output? I am trying to avoid an extra A/D step here, but I have no experience with it. Post-filter, I am satisfied that a simple one-bit D/A with passive filtering will get me to 16 bits resolution for the VCXO control, enough for ppb resolution. Thanks for the data point on the vcxo thermal sensitivity; it's very useful! Regards, Mark Said Jackson [saidj...@aol.com] wrote: > Stephane, you will need to replace the analog low-pass filter that follows > the phase comparator with a digital low pass filter to get 0.1Hz or lower > loop bandwidth. This is what a GPSDO does. A simple PID loop is what > accomplishes this typically. [...] > On the thermal sensitivity of that Crystek vcxo: it is slow enough for > even a loop with 0.1Hz BW to compensate for it easily if you shield the > crystal from airflow. _______________________________________________ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
