Hi Bob, The job done by linear regression is to reduce the uncertainty. This counter is designed to use continous timestamp method. My current design can measure 9000 times/second. If I only use the 1st and last one to calculate, it's the traditional recipocal + interploator method. This is what you can see on the chart named "without linear regression". The uncertainty of slope(the frequency ratio of ref and signal ) is contributed by these 2 measurements. With linear regression of all 9000 data within one second, the uncertainty will reduced to smaller one. (I really can't remember the ratio. Something like sqrt(9000)).
while(1) { double t3; //fraction part of refcnt, measured by tdc_gp22 double ref_curr; uint32_t sig_curr; static double ref_start; static uint32_t sig_start; uint32_t refcnt, sigcnt; const uint32_t gate_time = 1000; // 1000ms gate time if (i == 0) { init_regression(&rv); cpld_rst(); timestamp(&refcnt, &sigcnt, &t3); ref_start = refcnt - t3; sig_start = sigcnt; i++; continue; } timestamp(&refcnt, &sigcnt, &t3); regression_enter_data(&rv, refcnt - t3 - ref_start, sigcnt - sig_start); if (msecond < gate_time) { i++; continue; } else { t = regression_slope(&rv) ; // with linear regression printf("\r\nFreq=%.*f", 14, t); ref_curr = refcnt - t3; sig_curr = sigcnt; t = CalcFreq(ref_curr - ref_start, sig_curr - sig_start); // without linear regression printf(" Interpolated=%.*f", 12, t); msecond = 0; i = 0; } } 2014-12-12 21:18 GMT+08:00 Bob Camp <kb...@n1k.org>: > > HI > > > On Dec 12, 2014, at 4:04 AM, Tom Van Baak <t...@leapsecond.com> wrote: > > > > This large posting is from Li Ang. > > /tvb > > > > ----- Original Message ----- > > From: Li Ang > > To: Discussion of precise time and frequency measurement > > Sent: Thursday, December 11, 2014 7:37 AM > > Subject: Re: [time-nuts] Homebrew frequency counter, need help > > > > > > Hi Bob, > > I've sent the PCB to the factory and I am waiting for the new board. > This time, it's a 4-layer borad and changed from CPLD to FPGA. This is the > first time of FPGA & 4-layer project. Hope everthing be OK. > > Very nice looking. I hope it works !!! > > > TPS79333 as the LDO for TDC. Better PSRR and noise spec than before > (XC6206). Analog and digital parts have their dedicated LDO. > > > > > > While I'm waiting the the new board. I did a test with PRS10 & FE5650 > with current board. It's strange that the 20s adev of "without linear > regression" is better than "with linear regression” > > Be careful pre-processing ADEV data. There are a variety of statistical > “traps” you can fall into. An overly simple explanation is that ADEV looks > at noise and that most pre-processing is a filter. Filters take out noise. > Finding one that only takes out the “bad noise” and keeps the “good noise” > can be quite difficult. > > What exactly are you doing in your linear regression computation? > > Bob > > > > .<bottom_layer.GIF><power_plane.GIF><top_layer.GIF><adev.gif>_______________________________________________ > > time-nuts mailing list -- time-nuts@febo.com > > To unsubscribe, go to > https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts > > and follow the instructions there. > > _______________________________________________ > time-nuts mailing list -- time-nuts@febo.com > To unsubscribe, go to > https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts > and follow the instructions there. > _______________________________________________ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.