j...@febo.com said: > Per Tom Clark, who came up with the idea, they are *not* intended to > provide a near-end line termination to 50 ohms, but are simply there to > protect the paralleled devices if the gates have slightly different delays > (in which case one gate could end up sinking the other two).
Is that a real problem? How far off can the prop delay be for 2 gates on the same chip? I seem to remember reading something saying it was OK to just wire them up in parallel. It could have been an app note, or it could have been a rumor on usenet. -- These are my opinions. I hate spam. _______________________________________________ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.