Hi,
Another method would be to measure the phase-detector beat-note
frequency (most have mixer-like behavior), which you should be able to
measure with quite good precision, then set the EFC accordingly and then
close the loop.
If you measure for sufficient time, and fail to detect a beat-note, then
it will be close enough in frequency for the PLL to lock to it anyway.
Pre-setting the state of the integrator like this is relatively simple
and straight-forward.
If you have an oven, it is wise to discard beat-note frequencies outside
of some suitable range, so that it first needs to go within that range
before any attempt to lock it is done, so that worst part of the heat-up
frequency deviation and drift has ended. If you don't do that, you need
to set your time-constant short for the memory effect to wear off
quickly and then the filtering won't be optimum for GPS noise.
You need to have a conversion factor for converting frequency error to
EFC steering, and part of this factor will be the actual EFC
sensitivity. Trimming this factor will reduce the residue frequency
error after setting, so monitoring it and trimming the factor can be
done if one wants to improve lock-up time, but as long as it is
relatively near, it's really not that critical.
Cheers,
Magnus
On 09/26/2015 03:14 PM, Bob Camp wrote:
Hi
Why not do a FLL based on the counter and let the TDC run at 5 MHz (with 5X
the resolution)?
It’s reasonable to believe that if you run the FLL for a while you will get
things
quite close. That should allow you to run the TDC at 10 MHz.
Bob
On Sep 26, 2015, at 7:22 AM, Jim Harman <j99har...@gmail.com> wrote:
Good question Will.
First, it divides the 10 MHz down to 1 MHz, so the oscillator would have to
be off by 10 Hz for it to lock onto the wrong cycle.
Second, the full implementation also feeds 5 MHz from the oscillator into
one of the processor's counters and checks the count every second. It
performs several checks on this to detect if the frequency is way off,
missed PPS, etc.
On Sat, Sep 26, 2015, 12:15 AM Will <zl1...@gmx.com> wrote:
Hi,
I'm new and trying to get to grips with things.
If I understand correctly, please forgive if I have it wrong, This
locks a 10MHz signal to a 1Hz (1pps) signal. What makes it lock to 10
000 000Hz instead of 999 999Hz or 10 000 001Hz? Just the hope that the
10MHz is exactly that?
Cheers,
Will
On 26/09/15 08:32, Jim Harman wrote:
To further demonstrate the Diode - R- C- approach, here (hopefully) is a
screenshot of the raw DAC output vs time on my Arduino Micro (32u4) based
system. For this test the oscillator is free running with an error of
about
1 usec per 460 sec or 2.17x10^-9. The horizontal scale is 125 sec/div
(1000
sec total) and the vertical is 1024 DAC counts (0-2.56 V) which
corresponds to 1 usec of offset between the oscillator and the reference.
You can see that there is some curvature because the capacitor is being
charged through a resistor and not a true current source, but as I
mentioned earlier this does not affect the system's ability to lock the
oscillator to the pps reference. When locked with a time constant of 1000
sec, the phase detector output is almost always less than +/- 100 counts
from the setpoint of 500.
The noise is due mostly to jitter in my PPS reference, which is generated
by an Adafruit GPS module. Presumably it would be less if I had a real
timing receiver.
.
If the inserted image does not come through, I will re-send as an
attachment.
--
--Jim Harman
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