There's the small matter of the high phase shift tempco of the narrow 10MHz
bandpass filters Q~10,000 or so.These would need to either track very closely
or be in an oven with very high temperature stability.The PN contribution of
these analog filters may also be an issue.
Bruce
On Thursday, 21 April 2016 9:03 AM, Attila Kinali <att...@kinali.ch> wrote:
On Wed, 20 Apr 2016 07:17:58 -0700
Nick Sayer via time-nuts <time-nuts@febo.com> wrote:
> I spent some time yesterday mashing together my FE-5680A "breakout" board
> with my GPSDO to make a GPS discipline board for it. Before I send the board
> off to OSHPark, I'd like to open the design to criticism (and I mean that in
> its neutral sense) here first.
Looking at your schematics, I would replace the input squarer (IC4)
by something different than a schmitt-trigger with an input bias
voltage. For one, schmitt-triggers are more noisy than normal buffers
for an other, the bias voltage will result in a slightly skewed duty
cycle. If you want to use a gate, then the canoncical way would be to
use an inverter with an input capacitor like you did, but let it self-bias
itself by using a 100k-1M resistor from its output to its input.
Important: don't use a buffer, as this will only work with an inverter.
But I'd rather use a different squaring circuit, if you want to use
the input directly for the output. There are many discussions on
squaring circuits in the archives. Probably the most simple, yet sofisticated
is the one you can find in the TADD-2.
But:
As you can see on http://www.ke5fx.com/rb.htm the phase noise of the
FE 5680's is horrible at best, hence I wouldn't use it as source for
anything directly. Additionally, the tuning word you write through
the RS-232 is stored in an EEPROM inside the FE-5860 (unless i mix
it up with another Rb). Writing this tuning word often will wear out
the EEPROM pretty quickly. Hence you should not do this too often.
What I would do instead is, use your current GPSDO design, with OCXO
and all, but add something with which you can measure the phase/frequency
of an external 10MHz reference. One way would be to use a digital DMTD[1,2]..
Another would be to sample the reference using an ADC and build DMTD in
the digital domain. For this you wouldn't need a high sampling rate, a
couple of kHz should be enough, as long as the analog bandwidth of the
ADC is high enough (>10MHz, better >20MHz). What you need is some PLL
though, as you need to create a frequency that is not an integer divisible
of 10MHz, as the ADC clock is used to downmix the reference frequency.
Eg:
If you can generate a 10001Hz ADC sampling clock from the OCXO,
you will get a 1kHz beat frequency. You can "lock" to this using a
digital PLL combined with an NCO (numerically controlled oscillator).
Then use the steering word for the NCO as an input for the control
loop of the OCXO, toghether with the corrections calculated from the
GPS PPS.
The advantage of this is, that you get the low phase noise and good
short term stability of the OCXO, but can use the Rb to get the nice
mid-term stability (somewhere from 1 to 10s up) while getting the
accuracy of a GPSDO, whithout ever the need of writing to the tuning
word of the Rb. That keeps your Rb more stable (the internal conditions
of the Rb do not change) and allows you to compensate for quite large
frequency offsets for Rb refernces that are working outside the spec,
but are otherwise fine.
One thing that you have to take care of is spurs, though. Because
the ADC does some heavy down-mixing, or rather sub-sampling, this
approach is quite sensitive to spurs. In order to not introduce some
weird oscillations in the control loop due to spurs in the reference
signal, you should use some narrow 10MHz filter at the input (at most
half the sampling frequency wide). One way to achieve that is using a
ceramic resonator which are available at 10MHz.
Attila Kinali
PS: I'm pretty sure I am not the first one with this idea. But I have never
seen anyone else mention it, much less implement it. Does anyone know why?
[1] "Digital Dual Mixer Time Difference for Sub-Nanosecond Time
Synchronization in Ethernet", by Moreira, Alvares, Serrano, Darwezeh and
Wlostowski, 2010
[2] "Digital femtosecond time difference circuit for CERN's timing system",
by Moreira, Darwazeh, 2011
http://www.ee.ucl.ac.uk/lcs/previous/LCS2011/LCS1136.pdf
--
Reading can seriously damage your ignorance.
-- unknown
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