Hi Attila,
On 05/03/2016 02:31 PM, Attila Kinali wrote:
Hi,
We had here a discussion about measuring events (ie time stamping
them precisely) with high rates. As some of you know, Javier and
his group, Bruce and me are working on a system that should give
us something better than 10ps (my guess is that we should get close
to 1ps) at a rate of (guestimated) 1MHz per channel. (Based on the
excitation of a LC tank and measuring the ring-down/phase with an ADC).
As it is with researches, we want the moon, and prossible even more.
So we were talking about getting the measurement rate up even higher,
to 10MHz and if possible 50MHz with the same precision. The above
approche will not work above 1MHz. Using different filters it might
be possible to get it up to maybe 10MHz, but it would be an awkward
design at best.
Getting to those rates will be challenging, especially with the LC tank.
For the higher rates a more traditional interpolator needs to be used,
charge a cap with the error pulse and sample that.
The only methods I am aware of (and could find) that achieve such high
rates are those, based on (vernier) delay lines (and their equivalent
ring oscillator ones) in ASICs. But this means that a costly ASIC needs
to be produced.
13.3 MHz (or every 75 ns) is achievable with the HP5372A, but it had
relatively meager single-shot resolution, 200 ps, compared to its
predecessor. It uses the delay vernier approach rather than the
triggered oscillator vernier (HP5370A/B) just because of sample-rate.
The HP5371A/5372A is made to analyze jitter rather than high resolution
long term stuff. Even as the limit shifts over time, high speed will end
up having somewhat lower resolution than a lower rate could offer.
However, with higher rate, you can use the least-square methods of mine
to get results and fight the white noise that way.
Does someone know of other methods that could achieve high measurements
rates with better than 10ps precision/accuracy? (This question is mostly
a hypothetical question out of interest, I don't plan to build one...yet :-)
Well, if you sample at sufficiently high rate, you can estimate the
rising/falling edge using least-square methods and then interpolate the
position. There is only a relatively small burst of samples needed, and
the least-square processing can be done using high-speed FPGA methods
similar to what is found in the article I sent you.
An alternative to the edge estimator method is to continuously sample,
mix with a reference frequency, decimate and then do arc-tangent of the
I/Q samples. This is what is used for phase-noise measurement such as
the Symmetricom/Microsemi test-kits, TimePod, and also the new R&S
phase-noise system. The phase values can be produced at very high rates
there and the noise of such setups can be maintained relatively low
compared to the comparator systems. For such systems the noise per
phase-sample is maybe even better understood as the averaging time over
the phase vs. noise is relatively simple process to understand.
Pipeline CORDIC can be used for arctan processing.
Cheers,
Magnus
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