On 5/27/16 6:15 PM, Bob Camp wrote:
Hi
On May 27, 2016, at 8:17 PM, Bruce Griffiths <bruce.griffi...@xtra.co.nz> wrote:
On Thursday, May 26, 2016 06:40:26 PM Bob Camp wrote:
Hi
Very interesting paper, thanks for sharing !!
One question:
In many DMTD (and single mixer) systems, a lowpass and high pass filter are
applied to the signal coming out of the mixer. This is done to improve the
zero crossing detection. It also effectively reduces the “pre detection”
bandwidth. My understanding of the setup in your paper does not do this
sort of filtering. It simply operated directly on the downconverter signal.
Is this correct? I may have missed something really obvious in a quick
read of the paper…..
Thanks!
Bob
All the filtering and down mixing is done in the digital domain.
Anitialiasing filters in front of the ADCs are also be required.
A 2 (or more) receive channel SDR board would be a nice tool to use for this
provided the FPGA is large enough.
So … is there an explicit high pass in the FPGA other than the dc offset
elimination high pass?
There is obviously a lowpass function in the decimating FIR’s and the CIC. That
appears to be
optimized simply for sample rate rather than for noise. Thus the same question
applies to
low pass as well.
If they are using the stock USRP load, it's a digital down converter:
NCO mixes with input samples, CIC decimator and bandpass filter
(actually low pass I/Q), followed by a couple FIR filters.
Then, you can implement whatever further filtering and processing you
want in software, most commonly done in gnuradio (by far most common) or
simulink/Matlab.
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