> The designers very well designed two near inifinite counter chains inside the 
> 5335A..
> I got my wisdom from the hp journal 9-1980.

http://www.hpl.hp.com/hpjournal/pdfs/IssuePDFs/1980-09.pdf


> They used a digital ASIC, called the MRC, multi-register counter, and it 
> allows counting
> of the input signal and the time base, each 20 decades long. (see page 26).

Just to be clear, the MRC itself has only 8 decades. You get additional decades 
with off-chip processing, which is to say, counting overflows. It's the same 
way we keep 64-bit time in a microcontroller: 16 bits of timer and then 48 more 
bits of overflow count.

    "Another feature of the MRC lets its internal eight-decade
    count chains be expanded to any number of decades with
    the help of a processor. This feature is used to create a pair of
    count chains, each 20 decades long. With a 100-MHz signal,
    this chain would take more than 30,000 years to overflow.
    Consequently, the 5335A has no overflow annunciator, so
    gate times can be as short as 0 ns or as long as years."


There's more good info on the MRC starting on page 12 of an earlier HP journal:

"A High-Performance Bipolar LSI Counter Chip Using EFL and I2L circuits"
http://www.hpl.hp.com/hpjournal/pdfs/IssuePDFs/1979-01.pdf


The heritage of the MRC shows up in my picPET (Precision Event Timer). Notice 
how hp's MRC also has an E-register (Event) and a T-register (Time). Once you 
have matched {event count, time stamp} pairs anything is possible. By 
"anything" I mean, totalizing, absolute time, time interval, frequency, period, 
mean frequency, period average, best fit frequency, sigma, sigma(tau), ADEV, 
etc.

BTW, if any hp old-timers reading this posting happen to have detailed 
information on the 40-year old proprietary MRC chip, please contact me off-list 
before it's too late. By too late I mean:

http://www.pressdemocrat.com/business/7559762-181/hewlett-packard-archives-at-keysight-destroyed

/tvb

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