Hi

If you only run over 10% of the EFC range, you only gain 3 bits. If the 
objective is 
in the 22 bit vicinity, (maybe 20 maybe 22 …) you really don’t get enough bits 
at a 10% 
span. From a lot of years of playing with control loops, if you need 20 *good* 
bits, you better
have a few more than that in the design …. Indeed there are converters out 
there with 1/8
LSB performance. There also are a lot of them with “guaranteed monotonic” as 
the main spec.
In that case you may get 2 LSB of “jump” as you do this or that….

Indeed another alternative is to let the OCXO warm up for a month. Then adjust 
a pot to center
things up. Run a “fine range” ADC to keep it happy. Come back in three to nine 
months and 
tweak the pot again. The main risk is a power outage and waiting a few weeks to 
get things 
back up and running again. 

A lot of this depends on how much of an EFC range you have and how much aging 
you expect. 
If you have 4 PPM of EFC and expect 1x10^-9 per month that gets you a pretty 
small range. If
you have 5x10^-8 of EFC and expect 1x10^-9 per day, the entire EFC may not last 
you for very
long at all. 

Another factor is temperature. Your OCXO may be happy at 1x10^-11 / C. If your 
control circuit
is good at the 5x10^-10 / C level that may be ok or it may be a problem. Either 
way, your control
range needs to accommodate both the OCXO and the rest of the circuit on top of 
the aging. 

Bob

> On Nov 26, 2017, at 1:05 PM, Azelio Boriani <azelio.bori...@gmail.com> wrote:
> 
> ...and what about shrinking the 16bit over the fraction of the EFC
> range that, for example, the OCXO will be using for the next 5 years?
> 16bit over 10V are as 20 (a little less, OK) over 1V, if I can use my
> 16bit over 1V for the next 5 years, when the DAC will be near full
> scale I can "trim" the aging.
> 
> On Sun, Nov 26, 2017 at 6:25 PM, Bob kb8tq <kb...@n1k.org> wrote:
>> Hi
>> 
>> If you sum two DAC’s without any sort of feedback, you get problems when the
>> “coarse” dac is changed. You have no way to know the step size of the coarse
>> dac to (say) 20 bit precision.
>> 
>> As an example : If you are after 20 “good” bits, you might overlap
>> them at the 10 bit point on the coarse dac. That would give you 22 bits on 
>> the
>> summed output. It would give you enough extra bits to take care of any odd
>> things that might be going on. You only have 1/1024 of the total range before
>> you must tune the coarse dac. Even with a good set of parts, you *will* be
>> doing coarse tuning.
>> 
>> Bob
>> 
>>> On Nov 26, 2017, at 12:13 PM, Azelio Boriani <azelio.bori...@gmail.com> 
>>> wrote:
>>> 
>>> Is summing a "fine tune" 16bit DAC and a "coarse tune" 16bit (or less)
>>> DAC with an op-amp not good enough?
>>> 
>>> On Sun, Nov 26, 2017 at 5:53 PM, Bob kb8tq <kb...@n1k.org> wrote:
>>>> Hi
>>>> 
>>>> Each time I’ve tried the method in the app note, there has been a tone in 
>>>> the output
>>>> spectrum at the sample rate of the ADC. I’ve never found a way to do the 
>>>> grounding
>>>> that eliminates it. The tone is large enough to show up as a spur on a 
>>>> “typical” OCXO
>>>> when it goes into the EFC port.
>>>> 
>>>> Bob
>>>> 
>>>>> On Nov 26, 2017, at 8:56 AM, Ole Petter Rønningen <opronnin...@gmail.com> 
>>>>> wrote:
>>>>> 
>>>>> I guess everyone has seen this, but Linear has a nice appnote «A 
>>>>> Standards Lab Grade 20-Bit DAC with 0.1ppm/°C Drift»
>>>>> 
>>>>> http://cds.linear.com/docs/en/application-note/an86f.pdf
>>>>> 
>>>>> Ole
>>>>> 
>>>>>> 26. nov. 2017 kl. 13:50 skrev Magnus Danielson 
>>>>>> <mag...@rubidium.dyndns.org>:
>>>>>> 
>>>>>> Hi
>>>>>> 
>>>>>>> On 11/26/2017 02:26 PM, Attila Kinali wrote:
>>>>>>> Though, if you have a decent 16bit DAC and want to get to 18bit,
>>>>>>> that's fairly simple using delta-sigma modulation... if you can live
>>>>>>> with a low pass fillter after the DAC. But the DNL will be the limiting
>>>>>>> factor here (unless you use some special techniques) and the (absolute) 
>>>>>>> INL
>>>>>>> will not get better, for obvious reasons.
>>>>>> 
>>>>>> I needed 19 bit rather than 16 bit, so I implemented an interpolation 
>>>>>> scheme. A first degree sigma-delta would also be possible, but for low 
>>>>>> ratios what I did was more efficient.
>>>>>> 
>>>>>> A first degree sigma-delta is fairly simple thought.
>>>>>> 
>>>>>> The trick is that you want to push the noise high up so it becomes 
>>>>>> trivial to filter, then the filter will not be hard to design and won't 
>>>>>> be low enough to cause PLL instability and implementation troubles.
>>>>>> 
>>>>>> Cheers,
>>>>>> Magnus
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