It's not just that you need to have small signal Thevenin source impedance << 50 ohms, you also need to be able to deliver sufficient current, at the rated logic voltage swing of the device. If the device is swinging rail to rail, and you drive a 50 ohm load through a 50 ohm resistor in series with a blocking capacitor, the device has to be able to source and sink 16.5 mA. You can also estimate the Thevenin impedance from the data sheet numbers giving voltage swing vs current. You probably won't get rail to rail swing at 16.5 mA with your gate, or any other CMOS gate. In all likelihood, you will want to do something like use a 74__04 Hex Inverter with all 6 gates wired in parallel.
If you follow your driver with a bandpass filter, it should be a design that presents a high impedance to the driver at harmonic frequencies so the gate can be happy making a square wave of voltage. This gives an advantage of 4/pi in drive capability. Rick N6RK On 3/3/2018 4:09 AM, David C. Partridge wrote:
Using this to buffer output from an LPRO (74VHC1G14 (Schmitt trigger 3.3V TTL compatible)), or an Efratom 105243-003 10MHz OCXO with CMS output (74VHC1GU04 CMOS levels) in a 10MHz mod for the KS-24019 RFTGm-II. To match well to 50R bandpass I want to add a series resistor to the output but don't know the output impedance of these single logic gates. Does anyone know what this is please? _______________________________________________ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
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