Hi Most of the traditional rules about phase noise apply out to 10 or 20% of the “carrier” frequency. If the carrier is 1Hz, then you are talking about the traditional definitions holding out to 0.1 or 0.2 Hz relative to carrier. That’s *deep* in the 1/F noise part of the divider’s “noise curve”.
Since the ADEV of the 1 PPS is typically no worse than the ADEV of the 10 MHz, it would be hard to come up with a model where the 1 PPS has picked up a lot of extra noise. Bob > On Sep 15, 2018, at 9:05 PM, Scott Stobbe <scott.j.sto...@gmail.com> wrote: > > That is fascinating. So, the 1PPS line on a GPSDO (a divide by 10Meg in > many cases) is 70 dB worse than the traditional 20log(N) PN scaling? > > On Sat, Sep 15, 2018 at 11:40 AM Richard (Rick) Karlquist < > rich...@karlquist.com> wrote: > >> Another great posting from Attila that keeps the S/N ratio >> on this list high. >> >> On 9/15/2018 3:26 AM, Attila Kinali wrote: >> >>> possible logic family for the task. Otherwise the harmonics of the >>> switching of the FF will down-mix high frequency white noise down >>> to the signal band (this is the reason for the 10*log(N) noise scaling >>> of digital divider that Egan[1] and Calosso/Rubiola[2] and a few others >>> mentioned). >> >> Wow, I never knew this in 45 years of designing synthesizers! >> I do remember that some of the frequency counter engineers at HP >> talked about noise aliasing. I think this is another way of >> describing the same problem. >> >> About 10 years ago, the frequency synthesizer chip vendors started >> talking about a Figure of Merit (FOM) that predicted phase noise floor, >> and it also included the 10 LOG N noise scaling. An application >> engineer at ADI told me this was a characteristic of the sampling phase >> detector that all these chips used. But I always wondered if the >> frequency divider could come into play. The way FOM is defined, >> it doesn't distinguish between phase detector and divider noise. >> >> At Agilent, we used to make a lot of lab demos using a Centellax >> (now Microsemi AKA Microchip) frequency divider that could divide by any >> number between 8 and 511 up to 10 GHz. It was absolutely fabulous for >> dividing 10 GHz down to 2.5 GHz. But 20 LOG N quit working if I tried >> to divide down to 50 MHz. Now you have explained it. >>> >>> If you divide by something that is not a power of 2, then it is important >>> that each stage produces an output waveform with a 50% duty cycle. >> Otherwise >>> flicker noise which has been up-mixed by a previous stage, will be >> down-mixed >>> into the signal band, increasing the close-in phase-noise. >> >> Wow, another thing I never knew. The conventional wisdom was to >> divide by any number (even or odd) and then follow that divider >> with a divide by 2 flip flop to get 50%. Now, that is in question. >> The now correct answer is to us a variable modulus prescaler to >> divide by P and P+1, controlled by a toggle flip flop to make >> half the divisions at P and half at P+1. >> >> Does anyone else have experience with these issues? >> >> Rick N6RK >> >> >> _______________________________________________ >> time-nuts mailing list -- time-nuts@lists.febo.com >> To unsubscribe, go to >> http://lists.febo.com/mailman/listinfo/time-nuts_lists.febo.com >> and follow the instructions there. >> > _______________________________________________ > time-nuts mailing list -- time-nuts@lists.febo.com > To unsubscribe, go to > http://lists.febo.com/mailman/listinfo/time-nuts_lists.febo.com > and follow the instructions there. _______________________________________________ time-nuts mailing list -- time-nuts@lists.febo.com To unsubscribe, go to http://lists.febo.com/mailman/listinfo/time-nuts_lists.febo.com and follow the instructions there.