On 7/8/19 10:30 PM, Hal Murray wrote:
Not only are they low noise, but they have spectacularly good HF
rejection across the regulator up to 10s of MHz.
In the 5071A, I wanted high bandwidth PSRR and stumbled across a designer's
manual (HP internal document) for the MMS Modular Measurement System. They
described a regulator with a common base pass transistor and an op amp, with
a bandwidth approaching 1 MHz.
I'm used to thinking that the bypass caps on the board will take care of high
frequencies.
They're actually low pass filters - it's an RC or LC filter, with either
an explicit R or L, or just the parasitic R and L from the wiring.
When you need, say, 100 dB rejection, you can try and build a couple 60
dB Low pass filters (typically some sort of C L C pi network) in series,
or you can use a smaller filter followed by an LDO.
The filter approach has voltage drop that varies with the load current.
If you're feeding something like a MMIC amplifier (where the supply
feeds the drain/collector of a transistor and has essentially Zero
PSRR), you want a stable voltage because that sets the gain and P1dB - a
series RC/LC filter is a problem.
Essentially, the regulator provides a very low source impedance over a
wide band
What's the advantage of a PSRR in the MHz range? Is it as simple as reducing
the number and size of the caps needed?
and getting rid of variable voltage drop in the filter.
In this area, is there a significant difference between analog and digital
sections?
I would think so.. in digital circuitry, one typically isn't as
concerned about quiet supplies per se, except as it might affect the
thresholds, but you are concerned about the source impedance (ground
bounce and things like that)
For analog circuits, you need really quiet bias supplies, since a lot of
amplifiers have terrible inherent PSRR - consider a common emitter
circuit - noise on the base bias or collector bias basically goes right
to the output, perhaps with gain. The new LDO for negative voltages is
very attractive for FET circuits that need negative bias on the gate.
We designed and built a small HF receiver for a space application a
couple years ago (2017) that has a noise figure <3dB from 5-30 MHz - We
wanted to measure the galactic background noise, so the design
requirement was "receiver noise < galactic background with 6 meter long
dipole".
The way we got there from a noisy 12V battery bus, and with a big FPGA
drawing watts, and fast ADCS, was CLC filters going off the power
supply board with the buck converters, CLC filters going on the
downstream board, followed by a LT3042 to the RF circuits. And steel
shielding cans. We did fiddle around a bit with the intermediate
regulator voltages from the buck converters to make sure we could
accommodate the drops in the CLC filters - but that was changing a
single resistor or two.
BTW, boost converters are a lot noisier than buck converters, and
buck/boost designs that tolerate a wide input voltage swing change their
noise properties a LOT when transitioning from buck to boost.
I don't know if we could have left any of that out - we didn't have time
to do extensive experimentation, so there was definitely an air of
belt+suspenders+staples+duct tape in the design.
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