hm,

first example of divide by 5 needs an additional AND, second example gets stuck in an unused state :(

Cheers

Detlef

Am 01.07.2020 um 02:14 schrieb David:
Here's a web page with several JK flip-flop dividers, including divide
by 5:

http://www.play-hookey.com/digital/counters/frequency_dividers.html

Dave

On 2020-06-30 15:47, dschuecker wrote:

Hi,

a divide by five should possible with a synchronous state-machine made of 3 ( 
sufficiently fast-) JK-FlipFlops.

All 3 FFs are clocked with the input freq. , the outputs of the FFs are fed 
back to the the JK-inputs,  the divided freq. is output of one of the FFs.

Additional constraints: no external ANDs or ORs or NOTs, the state-machine does 
not get stuck in the 3 unused states.

This turned out to be a very interesting problem and I do not yet come up with 
a solution. Maybe there is none. Analytical solutions all failed, I will try a 
brute force enumeration attack tomorrow.

lots of fun !

Cheers

Detlef

Am 30.06.2020 um 08:37 schrieb Hal Murray: You might try the 74AC161, which 
works to 73MHz at 3.3V or 103 MHz at 5V, -40
to 85C.
Set the data inputs to DCBA = 1011 and connect an inverter from the carry
output (pin 15) to the Load input (pin 9) to divide by 5. See http://
www.techlib.com/electronics/74161Divider.htm [1] You didn't read the data sheet 
carefully enough.  That 73 MHz is the bragging
number for sales people, often not useful.  For something like this, you need
to add the clock-to-out for the ripple carry, prop time through inverter, and
setup time at the load input.

I was going to ask whether 73MHz included the delay through the inverter, but
it's much worse than that.  The clock to out on the RCO pin is 21 ns.  Even
without the inverter, it won't make 50 MHz.

You can save a few ns if you use a FF with inverting output instead of an
inverter.  That adds a pipeline stage so you have to adjust the constant that
gets loaded.  Setup time on a 3V AC74 is 4.3 ns which gets to 40 MHz (actually
only 39.5).

At 5V,
AC161 clk-RCO is 15.2
AC74 setup is 3.1
So that works - 54.6 MHz.

Using an inverter:
AC161 clk-RCO is 15.2
AC04 prop 5.9
AC161 setup 5.3
That's 37.9 MHz

(That's all assuming I didn't fatfinger anything.)

I like Richard Karlquist's trick of using a data bit to reload.
Unfortunately, for the AC161, the data out isn't significantly faster than the
carry out.

If I did the numbers correctly, that's 35 MHz at 3.3V and 49.3 MHz at 5V.
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Links:
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[1] http://www.techlib.com/electronics/74161Divider.htm
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