On Thu, Feb 4, 2021 at 4:09 PM Hal Murray <hmur...@megapathdsl.net> wrote: > In case anybody isn't familiar with ARM SOC chips, they typically have a layer > of muxes between the external pins and the internal I/O devices. I don't know > if the chip used in the Pi-4 works this way. Quite likely. > > > The system designer has to find a combination of mux settings that works for > the application. Leftover pins can be used as GPIO. And the clocking is > tangled up in there.
While true for many pins, usually quite a few are not muxed. Those deemed necessary for all designs or with specialized drivers. So typically there will be no mux for power pins, dram interface, xtal inputs, and high speed differential data, like USB3, PCIe, SGMII, MIPI CSI or DSI. Or perhaps muxing between different high speed serial interfaces. It seems to be very common for ARM SoC chips to be designed to be clocked by either an XTAL and a built in oscillator, or via an external clock generator connected to the same pin. But, I've never seen a SoC where this pin could be muxed. I've not seen one where the input clock frequency had much of a range. It might be 24-26 MHz, but never 10 - 52 MHz. At least documented. But the clock is invariably an input to a programmable PLL or PLLs, and those PLLs are likely programmable with a rather wider range of multipliers and dividers than required for the limited documented input frequency range. One might have better luck with a chip from Ti or NXP, since, unlike Broadcom, they have documentation on how their clocks and PLLs work. _______________________________________________ time-nuts mailing list -- time-nuts@lists.febo.com To unsubscribe, go to http://lists.febo.com/mailman/listinfo/time-nuts_lists.febo.com and follow the instructions there.