Am 22.11.21 um 18:31 schrieb Erik Kaashoek:
Some time ago I needed a output at 10,000000.001Hz so I tried to do that
with a SI5351.
Using pure integer math (as the PLL and divider register are integers) i
search for a combination of 3 divider/multipliers that gave the least
error.
If the reference frequency is not integer related to the internal PLL
frequency and multiplier/divider registers you always will have limited
accuracy as there is a fractional error.
The amount of error will depend on the number of digits in the
multiplier/divider register lengths and the care you take to search for
the best solution.
If the DDS has a PLL driven clock this could be the cause.
There once was a BCD DDS chip made by Standard Telecom.
Doing that in an FPGA would be an easy exercise.
Cheers, Gerhard
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