You can actually use a single small N channel MOSFET (2N7000 or similar)
with it's Gate connected to the lower Vcc via, say, a 1k resistor. (Not
strictly needed, but with long leads, it helps prevent HF transient
oscillation.
Then use it's Source as the lower voltage data line, and it's Drain as
the higher voltage data line. You get two way communication like that
too. (Hint: Consider the parasitic diode between the Drain and Source.)
Action: everything floats high to 3.3V or 5V. FET is not conducting.
Pull the 3.3V side down, FET turns on (Gate is +3.3V wrt Source) and the
Drain pulls down the 5V side, note the 5V side pull down current will
pass to the 3.3V side, so take care that the 3.3V pull down port is
capable of sinking that current as well...
Pull the 5.5V side down, Parasitic diode conducts, pulling down the 3.3V
side that in turn also turns on the FET, providing a lower impedance
path "backwards" though the device. As above, the 5V side "sinks" the
3.3V pull down current. It all works magically well.
Many of the simple multichannel bus voltage translators that do NOT
provide galvanic isolation, are just like that internally, but with pull
up's to the two Vcc rails, and some extra protection diodes etc.
I've done that between 3.3V and 5V systems, and between 5V and 9V logic
systems with discrete parts, It works very well indeed.
To a limited degree, the same "trick" also works with many bipolar
transistors, with a diode from Emitter to Collector, and a better choice
of resistor on the Base.
Have Fun.
Dave G8KBV
On 29/01/2022 08:30, time-nuts-requ...@lists.febo.com wrote:
I find that the best way to handle these translations is to use one of
TI's level translators ... each chip has two power supply rails, and
translation is done transparently across the chip, and there is good max
voltage overprotection on both sides as well. I use them a lot to handle
5V <-> 3.3V level issues.
Try the SN74LVC8T245PWR for unidirectional level translating . They also
have some bidirectional ones ...
--Andrew
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