huh...I don't see a spec for GPIO in the ATMEGA databook,
but the SPI diagrams indicate worst case rise times circa
250ns so I'd assume that you could keep up with ~500ns
pulse widths.
The fastest you can switch is one instruction cycle,
which is one clock cycle, which would give you a pulse
period of (2*(1/7.3728MHZ)) or about 270ns. So with
appropriate loop control and maybe a NOOP or two
it looks like at least .5 to 1Mhz...
Would need to hook up a scope and see if the capacitance on
the board contributes anything though.
MS
Neschae X. Fernando wrote:
Hi,
Does anyone know the maximum toggle (high to low and low to high) rate
of the GPIO pins for the Atmega 128L?
thanks
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