To: "Matthew J Whelan" <[EMAIL PROTECTED]>
From: "Matt Orlofsky" <[EMAIL PROTECTED]>
Date: 11/29/2005 04:00PM
cc: <[EMAIL PROTECTED]>
Subject: RE: [Tinyos-help] Tmote SCLK Change Effects DelugeMatt,Interesting. Is changing the clock rate in an application more complex then a simple write to BCSCTL2? If so, would you be willing to send me a code snippet?Thank you for the quick response.Matt Orlofsky
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RLW, Inc.
Phone: 814-689-1833
Cell: 585-233-8243
From: Matthew J Whelan [mailto:[EMAIL PROTECTED]
Sent: Tuesday, November 29, 2005 3:50 PM
To: Matt Orlofsky
Cc: [EMAIL PROTECTED]
Subject: Re: [Tinyos-help] Tmote SCLK Change Effects DelugeMatt,I have also developed applications in which I increased the SPI clock (SMLCK) to the MCLK rate for faster writting of data to the flash memory chip. I have had problems with using the SMLCK at the MCLK rate in my applications which do not use deluge. It appears to be related to the radio or UART transmission. If I change the rate to 4MHz only when writing to the flash and then revert back to 1MHz for radio communication I am ok though. Unless you are trying to communicate with the CC2420 at a faster SPI rate, I would suggest this approach, as I have not had any problems with this implementation.Regards,Matt[EMAIL PROTECTED] wrote: -----To: <[EMAIL PROTECTED]>
From: "Matt Orlofsky" <[EMAIL PROTECTED]>
Sent by: [EMAIL PROTECTED]
Date: 11/29/2005 03:39PM
Subject: [Tinyos-help] Tmote SCLK Change Effects DelugeAll,I changed MSP430ClockM.nc (see source code snippets below) such that the SCLK would run at the same speed as the MCLK (4MHz). I did this to improve the maximum clock rate of the SPI bus. The change appears to have worked in my application however Deluge does not work properly. I'm using Deluge 2.0. Any idea what the problem is? Perhaps there is a delay loop in the Deluge code that is effected by the change in clock rate? Any help would be greatly appreciated.// Snippet from MSP430ClockM.nc v1.14 near line 60//--------before--------//// BCSCTL2
// .SELM = 0; select DCOCLK as source for MCLK
// .DIVM = 0; set the divisor of MCLK to 1
// .SELS = 0; select DCOCLK as source for SCLK
// .DIVS = 2; set the divisor of SCLK to 4
// .DCOR = 0; select internal resistor for DCO
BCSCTL2 = DIVS1;//-------/before--------////---------after---------//// BCSCTL2
// .SELM = 0; select DCOCLK as source for MCLK
// .DIVM = 0; set the divisor of MCLK to 1
// .SELS = 0; select DCOCLK as source for SCLK
// .DIVS = 0; set the divisor of MSCLK to 1
// .DCOR = 0; select internal resistor for DCO
BCSCTL2 = 0x00;//--------/after---------//Matt Orlofsky
____________________
RLW, Inc.
Phone: 814-689-1833
Cell: 585-233-8243
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