There were some posts about pre-emptable interrupts a while ago
whose final conclusions I don't remember. But in general ints
on the ATMEGA are latched such that the second int will fire
when interrupts are re-enabled. The part I don't remember is
that there may be some level-only ints that do not carry over
if the signal is removed before being enabled. A very close
reading of the manual is called for to see where that might
be the case....
MS
roberto pagliari wrote:
I read the difference concerning the two macros TOSH_SIGNAL and
TOSH_INTERRUPT. Suppose that two interrupts are driven by the macro
TOSH_SIGNAL. Say
TOSH_SIGNAL( SIG1 )
{
// do something
}
TOSH_SIGNAL( SIG2 )
{
// do something
}
and suppose that sig1 happens. If in the meanwhile sig2 happens it
cannot interrupt sig1 ISR, but I read that some architectures remember
that interrupt and execute it afterwards. Does atmega remember an
interrupt if it happened during the ISR of another one, executing it
after the completion of ISR1?
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