On 9/13/24 4:56 PM, Ye Li wrote:
Chip erase support was added to spi_nor_erase, but the timeout
for polling SR ready is not updated and still for sector erase.
So the timeout value is not enough for chip erase on some NOR flash.
Follow kernel implementation 09b6a377687b ("mtd: spi-nor: scale up
timeout for full-chip erase") to set new timeout for chip erase.
Fixes: b91a0822d752 ("mtd: spi-nor: Add CHIP_ERASE optimization")
Signed-off-by: Ye Li <ye...@nxp.com>
---
Changes in v3:
- Replace spi_nor_wait_till_ready
Changes in v2:
- use do_div for u64
- Keep the variables in reverse xmas-tree
- Add kernel commit info
drivers/mtd/spi/spi-nor-core.c | 18 +++++++++++++++++-
1 file changed, 17 insertions(+), 1 deletion(-)
diff --git a/drivers/mtd/spi/spi-nor-core.c b/drivers/mtd/spi/spi-nor-core.c
index ce01d42cfe0f..1bddf7cf755f 100644
--- a/drivers/mtd/spi/spi-nor-core.c
+++ b/drivers/mtd/spi/spi-nor-core.c
@@ -45,6 +45,12 @@
#define DEFAULT_READY_WAIT_JIFFIES (40UL * HZ)
+/*
+ * For full-chip erase, calibrated to a 2MB flash (M25P16); should be scaled up
+ * for larger flash
+ */
+#define CHIP_ERASE_2MB_READY_WAIT_JIFFIES (40UL * HZ)
Why is DEFAULT_READY_WAIT_JIFFIES == CHIP_ERASE_2MB_READY_WAIT_JIFFIES ?
If that is correct, why do we need CHIP_ERASE_2MB_READY_WAIT_JIFFIES at
all ? It think it is best to remove CHIP_ERASE_2MB_READY_WAIT_JIFFIES
and always use DEFAULT_READY_WAIT_JIFFIES .
With that fixed:
Reviewed-by: Marek Vasut <ma...@denx.de>
Thanks !
