cpu/* parts of the patch.
--- /dev/null
+++ b/cpu/arm926ejs/at91cap9/Makefile
@@ -0,0 +1,46 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, [EMAIL PROTECTED]
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(SOC).a
+
+COBJS = ether.o serial.o timer.o spi.o usb.o
+SOBJS = lowlevel_init.o
+
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
+
+all: $(obj).depend $(LIB)
+
+$(LIB): $(OBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
--- /dev/null
+++ b/cpu/arm926ejs/at91cap9/config.mk
@@ -0,0 +1,5 @@
+PLATFORM_CPPFLAGS += -march=armv5te
+PLATFORM_CPPFLAGS += $(call cc-option,-mtune=arm926ejs,)
+# gcc version 4.2.1 (CodeSourcery Sourcery G++ Lite 2007q3-51) has some issues
+# with -Os: net/net.c:NetReceive() gets miscompiled. Switch to -O2 for now.
+PLATFORM_CPPFLAGS += -O2
--- /dev/null
+++ b/cpu/arm926ejs/at91cap9/ether.c
@@ -0,0 +1,35 @@
+/*
+ * (C) Copyright 2007
+ * Stelian Pop <[EMAIL PROTECTED]>
+ * Lead Tech Design <www.leadtechdesign.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/arch/AT91CAP9.h>
+
+extern int macb_eth_initialize(int id, void *regs, unsigned int phy_addr);
+
+#if defined(CONFIG_MACB) && defined(CONFIG_CMD_NET)
+void at91cap9_eth_initialize(bd_t *bi)
+{
+ macb_eth_initialize(0, (void *)AT91C_BASE_MACB, 0x00);
+}
+#endif
--- /dev/null
+++ b/cpu/arm926ejs/at91cap9/lowlevel_init.S
@@ -0,0 +1,43 @@
+/*
+ * AT91CAP9 setup stuff
+ *
+ * (C) Copyright 2007
+ * Stelian Pop <[EMAIL PROTECTED]>
+ * Lead Tech Design <www.leadtechdesign.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <version.h>
+
+#ifndef CONFIG_SKIP_LOWLEVEL_INIT
+
+.globl lowlevel_init
+lowlevel_init:
+
+ /*
+ * Clocks/SDRAM initialization is handled by at91bootstrap,
+ * no need to do it here...
+ */
+ mov pc, lr
+
+ .ltorg
+
+#endif /* CONFIG_SKIP_LOWLEVEL_INIT */
--- /dev/null
+++ b/cpu/arm926ejs/at91cap9/serial.c
@@ -0,0 +1,107 @@
+/*
+ * (C) Copyright 2007
+ * Stelian Pop <[EMAIL PROTECTED]>
+ * Lead Tech Design <www.leadtechdesign.com>
+ *
+ * (C) Copyright 2002
+ * Lineo, Inc <www.lineo.com>
+ * Bernhard Kuhn <[EMAIL PROTECTED]>
+ *
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <[EMAIL PROTECTED]>
+ *
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Alex Zuepke <[EMAIL PROTECTED]>
+ *
+ * Copyright (C) 1999 2000 2001 Erik Mouw ([EMAIL PROTECTED])
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ *
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/hardware.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#if !defined(CONFIG_DBGU) && !defined(CONFIG_USART0) &&
!defined(CONFIG_USART1) && !defined(CONFIG_USART2)
+#error must define one of CONFIG_DBGU or CONFIG_USART0 or CONFIG_USART1 or
CONFIG_USART2
+#endif
+
+/* ggi thunder */
+#ifdef CONFIG_DBGU
+AT91PS_USART us = (AT91PS_USART) AT91C_BASE_DBGU;
+#endif
+#ifdef CONFIG_USART0
+AT91PS_USART us = (AT91PS_USART) AT91C_BASE_US0;
+#endif
+#ifdef CONFIG_USART1
+AT91PS_USART us = (AT91PS_USART) AT91C_BASE_US1;
+#endif
+#ifdef CONFIG_USART2
+AT91PS_USART us = (AT91PS_USART) AT91C_BASE_US2;
+#endif
+
+void serial_setbrg (void)
+{
+ int baudrate;
+
+ if ((baudrate = gd->baudrate) <= 0)
+ baudrate = CONFIG_BAUDRATE;
+ /* MASTER_CLOCK/(16 * baudrate) */
+ us->US_BRGR = (AT91C_MASTER_CLOCK >> 4) / (unsigned)baudrate;
+}
+
+int serial_init (void)
+{
+ serial_setbrg ();
+
+ us->US_CR = AT91C_US_RSTRX | AT91C_US_RSTTX;
+ us->US_CR = AT91C_US_RXEN | AT91C_US_TXEN;
+ us->US_MR =
+ (AT91C_US_CLKS_CLOCK | AT91C_US_CHRL_8_BITS |
+ AT91C_US_PAR_NONE | AT91C_US_NBSTOP_1_BIT);
+ us->US_IMR = ~0ul;
+ return (0);
+}
+
+void serial_putc (const char c)
+{
+ if (c == '\n')
+ serial_putc ('\r');
+ while ((us->US_CSR & AT91C_US_TXRDY) == 0);
+ us->US_THR = c;
+}
+
+void serial_puts (const char *s)
+{
+ while (*s) {
+ serial_putc (*s++);
+ }
+}
+
+int serial_getc (void)
+{
+ while ((us->US_CSR & AT91C_US_RXRDY) == 0);
+ return us->US_RHR;
+}
+
+int serial_tstc (void)
+{
+ return ((us->US_CSR & AT91C_US_RXRDY) == AT91C_US_RXRDY);
+}
--- /dev/null
+++ b/cpu/arm926ejs/at91cap9/spi.c
@@ -0,0 +1,125 @@
+/*
+ * Driver for ATMEL DataFlash support
+ * Author : Hamid Ikdoumi (Atmel)
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+#include <config.h>
+#include <common.h>
+#include <asm/hardware.h>
+
+#ifdef CONFIG_HAS_DATAFLASH
+#include <dataflash.h>
+
+#define AT91C_SPI_CLK 10000000 /* Max Value = 10MHz to be compliant to
+ the Continuous Array Read function */
+
+/* AC Characteristics */
+/* DLYBS = tCSS = 250ns min and DLYBCT = tCSH = 250ns */
+#define DATAFLASH_TCSS (0xFA << 16)
+#define DATAFLASH_TCHS (0x8 << 24)
+
+#define AT91C_TIMEOUT_WRDY 200000
+#define AT91C_SPI_PCS0_DATAFLASH_CARD 0xE /* Chip Select 0: NPCS0%1110 */
+#define AT91C_SPI_PCS3_DATAFLASH_CARD 0x7 /* Chip Select 3: NPCS3%0111 */
+
+/*-------------------------------------------------------------------*/
+/* SPI DataFlash Init */
+/*-------------------------------------------------------------------*/
+void AT91F_SpiInit(void)
+{
+ /* Reset the SPI */
+ AT91C_BASE_SPI0->SPI_CR = AT91C_SPI_SWRST;
+
+ /* Configure SPI in Master Mode with No CS selected !!! */
+ AT91C_BASE_SPI0->SPI_MR =
+ AT91C_SPI_MSTR | AT91C_SPI_MODFDIS | AT91C_SPI_PCS;
+
+ /* Configure CS0 */
+ AT91C_BASE_SPI0->SPI_CSR[0] =
+ AT91C_SPI_CPOL | (AT91C_SPI_DLYBS & DATAFLASH_TCSS) |
+ (AT91C_SPI_DLYBCT & DATAFLASH_TCHS) |
+ ((AT91C_MASTER_CLOCK / (2*AT91C_SPI_CLK)) << 8);
+}
+
+void AT91F_SpiEnable(int cs)
+{
+ switch(cs) {
+ case 0: /* Configure SPI CS0 for Serial DataFlash AT45DBxx */
+ AT91C_BASE_SPI0->SPI_MR &= 0xFFF0FFFF;
+ AT91C_BASE_SPI0->SPI_MR |=
+ ((AT91C_SPI_PCS0_DATAFLASH_CARD<<16) & AT91C_SPI_PCS);
+ break;
+ case 3:
+ AT91C_BASE_SPI0->SPI_MR &= 0xFFF0FFFF;
+ AT91C_BASE_SPI0->SPI_MR |=
+ ((AT91C_SPI_PCS3_DATAFLASH_CARD<<16) & AT91C_SPI_PCS);
+ break;
+ }
+
+ /* SPI_Enable */
+ AT91C_BASE_SPI0->SPI_CR = AT91C_SPI_SPIEN; }
+
+/*---------------------------------------------------------------------------*/
+/* \fn AT91F_SpiWrite */
+/* \brief Set the PDC registers for a transfert
*/
+/*---------------------------------------------------------------------------*/
+unsigned int AT91F_SpiWrite ( AT91PS_DataflashDesc pDesc )
+{
+ unsigned int timeout;
+
+ pDesc->state = BUSY;
+
+ AT91C_BASE_SPI0->SPI_PTCR = AT91C_PDC_TXTDIS + AT91C_PDC_RXTDIS;
+
+ /* Initialize the Transmit and Receive Pointer */
+ AT91C_BASE_SPI0->SPI_RPR = (unsigned int)pDesc->rx_cmd_pt ;
+ AT91C_BASE_SPI0->SPI_TPR = (unsigned int)pDesc->tx_cmd_pt ;
+
+ /* Intialize the Transmit and Receive Counters */
+ AT91C_BASE_SPI0->SPI_RCR = pDesc->rx_cmd_size;
+ AT91C_BASE_SPI0->SPI_TCR = pDesc->tx_cmd_size;
+
+ if ( pDesc->tx_data_size != 0 ) {
+ /* Initialize the Next Transmit and Next Receive Pointer */
+ AT91C_BASE_SPI0->SPI_RNPR = (unsigned int)pDesc->rx_data_pt ;
+ AT91C_BASE_SPI0->SPI_TNPR = (unsigned int)pDesc->tx_data_pt ;
+
+ /* Intialize the Next Transmit and Next Receive Counters */
+ AT91C_BASE_SPI0->SPI_RNCR = pDesc->rx_data_size ;
+ AT91C_BASE_SPI0->SPI_TNCR = pDesc->tx_data_size ;
+ }
+
+ /* arm simple, non interrupt dependent timer */
+ reset_timer_masked();
+ timeout = 0;
+
+ AT91C_BASE_SPI0->SPI_PTCR = AT91C_PDC_TXTEN + AT91C_PDC_RXTEN;
+ while(!(AT91C_BASE_SPI0->SPI_SR & AT91C_SPI_RXBUFF) &&
+ ((timeout = get_timer_masked() ) < CFG_SPI_WRITE_TOUT));
+ AT91C_BASE_SPI0->SPI_PTCR = AT91C_PDC_TXTDIS + AT91C_PDC_RXTDIS;
+ pDesc->state = IDLE;
+
+ if (timeout >= CFG_SPI_WRITE_TOUT){
+ printf("Error Timeout\n\r");
+ return DATAFLASH_ERROR;
+ }
+
+ return DATAFLASH_OK;
+}
+#endif
--- /dev/null
+++ b/cpu/arm926ejs/at91cap9/timer.c
@@ -0,0 +1,165 @@
+/*
+ * (C) Copyright 2007
+ * Stelian Pop <[EMAIL PROTECTED]>
+ * Lead Tech Design <www.leadtechdesign.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/arch/hardware.h>
+
+/*
+ * We're using the AT91CAP9 PITC in 32 bit mode, by
+ * setting the 20 bit counter period to its maximum (0xfffff).
+ */
+#define TIMER_LOAD_VAL 0xfffff
+#define READ_RESET_TIMER (p_pitc->PITC_PIVR)
+#define READ_TIMER (p_pitc->PITC_PIIR)
+#define TIMER_FREQ (AT91C_MASTER_CLOCK << 4)
+#define TICKS_TO_USEC(ticks) ((ticks) / 6)
+
+ulong get_timer_masked (void);
+ulong resettime;
+
+AT91PS_PITC p_pitc;
+
+/* nothing really to do with interrupts, just starts up a counter. */
+int interrupt_init (void)
+{
+ p_pitc = AT91C_BASE_PITC;
+
+ /*
+ * Enable PITC Clock
+ * The clock is already enabled for system controller in boot
+ */
+ *AT91C_PMC_PCER = 1 << AT91C_ID_SYS;
+
+ /* Enable PITC */
+ p_pitc->PITC_PIMR = AT91C_PITC_PITEN;
+
+ /* Load PITC_PIMR with the right timer value */
+ p_pitc->PITC_PIMR |= TIMER_LOAD_VAL;
+
+ reset_timer_masked();
+
+ return 0;
+}
+
+/*
+ * timer without interrupts
+ */
+
+static inline ulong get_timer_raw(void)
+{
+ ulong now = READ_TIMER;
+ if (now >= resettime)
+ return now - resettime;
+ else
+ return 0xFFFFFFFFUL - (resettime - now) ;
+}
+
+void reset_timer_masked (void)
+{
+ resettime = READ_TIMER;
+}
+
+ulong get_timer_masked (void)
+{
+ return TICKS_TO_USEC(get_timer_raw());
+
+}
+
+void udelay_masked(unsigned long usec)
+{
+ ulong tmp;
+
+ tmp = get_timer(0);
+ while (get_timer(tmp) < usec) /* our timer works in usecs */
+ ; /* NOP */
+}
+
+void reset_timer (void)
+{
+ reset_timer_masked ();
+}
+
+ulong get_timer(ulong base)
+{
+ ulong now = get_timer_masked();
+
+ if (now >= base)
+ return now - base;
+ else
+ return TICKS_TO_USEC(0xFFFFFFFFUL) - (base - now) ;
+}
+
+void udelay(unsigned long usec)
+{
+ udelay_masked(usec);
+}
+
+/*
+ * This function is derived from PowerPC code (read timebase as long long).
+ * On ARM it just returns the timer value.
+ */
+unsigned long long get_ticks(void)
+{
+ return get_timer(0);
+}
+
+/*
+ * This function is derived from PowerPC code (timebase clock frequency).
+ * On ARM it returns the number of timer ticks per second.
+ */
+ulong get_tbclk (void)
+{
+ ulong tbclk;
+ tbclk = CFG_HZ;
+ return tbclk;
+}
+
+/*
+ * Reset the cpu by setting up the watchdog timer and let him time out
+ * on the AT91CAP9ADK board
+ */
+void reset_cpu (ulong ignored)
+{
+#ifdef CONFIG_DBGU
+ AT91PS_USART us = (AT91PS_USART) AT91C_BASE_DBGU;
+#endif
+#ifdef CONFIG_USART0
+ AT91PS_USART us = AT91C_BASE_US0;
+#endif
+#ifdef CONFIG_USART1
+ AT91PS_USART us = AT91C_BASE_US1;
+#endif
+#ifdef CONFIG_USART2
+ AT91PS_USART us = AT91C_BASE_US2;
+#endif
+
+ /*shutdown the console to avoid strange chars during reset */
+ us->US_CR = (AT91C_US_RSTRX | AT91C_US_RSTTX);
+
+ /* this is the way Linux does it */
+ *AT91C_RSTC_RCR = (0xA5 << 24) | AT91C_RSTC_PROCRST | AT91C_RSTC_PERRST;
+
+ while (1);
+ /* Never reached */
+}
--- /dev/null
+++ b/cpu/arm926ejs/at91cap9/usb.c
@@ -0,0 +1,64 @@
+/*
+ * (C) Copyright 2006
+ * DENX Software Engineering <[EMAIL PROTECTED]>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+
+#if defined(CONFIG_USB_OHCI_NEW) && defined(CFG_USB_OHCI_CPU_INIT)
+#ifdef CONFIG_AT91CAP9
+
+#include <asm/arch/hardware.h>
+
+int usb_cpu_init(void)
+{
+ /* Enable USB host clock. */
+ *AT91C_PMC_SCER = AT91C_PMC_UHP; /* 48MHz clock enabled for UHP
*/
+ *AT91C_PMC_PCER = 1 << AT91C_ID_UHP; /* Peripheral Clock Enable
Register */
+
+#if 0
+ /* The USB host controller must remain in reset. */
+ *AT91C_UHP_HcControl = 0;
+#endif
+
+ return 0;
+}
+
+int usb_cpu_stop(void)
+{
+#if 0
+ /* Put the USB host controller into reset. */
+ *AT91C_UHP_HcControl = 0;
+#endif
+
+ /* Initialization failed */
+ *AT91C_PMC_PCDR = 1 << AT91C_ID_UHP; /* Peripheral Clock Disable
Register */
+ *AT91C_PMC_SCDR = AT91C_PMC_UHP; /* 48MHz clock disabled for UHP
*/
+ return 0;
+}
+
+int usb_cpu_init_fail(void)
+{
+ return usb_cpu_stop();
+}
+
+#endif /* CONFIG_AT91CAP9 */
+#endif /* defined(CONFIG_USB_OHCI) && defined(CFG_USB_OHCI_CPU_INIT) */
--- a/cpu/arm926ejs/interrupts.c
+++ b/cpu/arm926ejs/interrupts.c
@@ -172,7 +172,7 @@ void do_irq (struct pt_regs *pt_regs)
bad_mode ();
}
-#ifdef CONFIG_INTEGRATOR
+#if defined(CONFIG_INTEGRATOR) || defined(CONFIG_AT91CAP9ADK)
/* Timer functionality supplied by Integrator board (AP or CP) */
--- a/cpu/arm926ejs/start.S
+++ b/cpu/arm926ejs/start.S
@@ -182,6 +182,9 @@ clbss_l:str r2, [r0] /* clear loop...
*/
cmp r0, r1
ble clbss_l
+ bl coloured_LED_init
+ bl red_LED_on
+
ldr pc, _start_armboot
_start_armboot:
--
Stelian Pop <[EMAIL PROTECTED]>
-------------------------------------------------------------------------
This SF.net email is sponsored by: Microsoft
Defy all challenges. Microsoft(R) Visual Studio 2008.
http://clk.atdmt.com/MRT/go/vse0120000070mrt/direct/01/
_______________________________________________
U-Boot-Users mailing list
[email protected]
https://lists.sourceforge.net/lists/listinfo/u-boot-users
