This patch fragment modifies the QE I/O pin configuration tables of all
relevant boards to include initial data.
Signed-off-by: David Saada <[EMAIL PROTECTED]>
mpc8323erdb/mpc8323erdb.c | 74 ++++++------
mpc832xemds/mpc832xemds.c | 74 ++++++------
mpc8360emds/mpc8360emds.c | 110 +++++++++---------
mpc8360erdk/mpc8360erdk.c | 280
+++++++++++++++++++++++-----------------------
mpc8568mds/mpc8568mds.c | 106 ++++++++---------
5 files changed, 322 insertions(+), 322 deletions(-)
--- a/board/freescale/mpc8323erdb/mpc8323erdb.c 2008-03-28
01:49:12.000000000 +0200
+++ b/board/freescale/mpc8323erdb/mpc8323erdb.c 2008-03-30
15:54:25.959133000 +0300
@@ -23,47 +23,47 @@
const qe_iop_conf_t qe_iop_conf_tab[] = {
/* UCC3 */
- {1, 0, 1, 0, 1}, /* TxD0 */
- {1, 1, 1, 0, 1}, /* TxD1 */
- {1, 2, 1, 0, 1}, /* TxD2 */
- {1, 3, 1, 0, 1}, /* TxD3 */
- {1, 9, 1, 0, 1}, /* TxER */
- {1, 12, 1, 0, 1}, /* TxEN */
- {3, 24, 2, 0, 1}, /* TxCLK->CLK10 */
-
- {1, 4, 2, 0, 1}, /* RxD0 */
- {1, 5, 2, 0, 1}, /* RxD1 */
- {1, 6, 2, 0, 1}, /* RxD2 */
- {1, 7, 2, 0, 1}, /* RxD3 */
- {1, 8, 2, 0, 1}, /* RxER */
- {1, 10, 2, 0, 1}, /* RxDV */
- {0, 13, 2, 0, 1}, /* RxCLK->CLK9 */
- {1, 11, 2, 0, 1}, /* COL */
- {1, 13, 2, 0, 1}, /* CRS */
+ {1, 0, 1, 0, 1, -1}, /* TxD0 */
+ {1, 1, 1, 0, 1, -1}, /* TxD1 */
+ {1, 2, 1, 0, 1, -1}, /* TxD2 */
+ {1, 3, 1, 0, 1, -1}, /* TxD3 */
+ {1, 9, 1, 0, 1, -1}, /* TxER */
+ {1, 12, 1, 0, 1, -1}, /* TxEN */
+ {3, 24, 2, 0, 1, -1}, /* TxCLK->CLK10 */
+
+ {1, 4, 2, 0, 1, -1}, /* RxD0 */
+ {1, 5, 2, 0, 1, -1}, /* RxD1 */
+ {1, 6, 2, 0, 1, -1}, /* RxD2 */
+ {1, 7, 2, 0, 1, -1}, /* RxD3 */
+ {1, 8, 2, 0, 1, -1}, /* RxER */
+ {1, 10, 2, 0, 1, -1}, /* RxDV */
+ {0, 13, 2, 0, 1, -1}, /* RxCLK->CLK9 */
+ {1, 11, 2, 0, 1, -1}, /* COL */
+ {1, 13, 2, 0, 1, -1}, /* CRS */
/* UCC2 */
- {0, 18, 1, 0, 1}, /* TxD0 */
- {0, 19, 1, 0, 1}, /* TxD1 */
- {0, 20, 1, 0, 1}, /* TxD2 */
- {0, 21, 1, 0, 1}, /* TxD3 */
- {0, 27, 1, 0, 1}, /* TxER */
- {0, 30, 1, 0, 1}, /* TxEN */
- {3, 23, 2, 0, 1}, /* TxCLK->CLK3 */
-
- {0, 22, 2, 0, 1}, /* RxD0 */
- {0, 23, 2, 0, 1}, /* RxD1 */
- {0, 24, 2, 0, 1}, /* RxD2 */
- {0, 25, 2, 0, 1}, /* RxD3 */
- {0, 26, 1, 0, 1}, /* RxER */
- {0, 28, 2, 0, 1}, /* Rx_DV */
- {3, 21, 2, 0, 1}, /* RxCLK->CLK16 */
- {0, 29, 2, 0, 1}, /* COL */
- {0, 31, 2, 0, 1}, /* CRS */
+ {0, 18, 1, 0, 1, -1}, /* TxD0 */
+ {0, 19, 1, 0, 1, -1}, /* TxD1 */
+ {0, 20, 1, 0, 1, -1}, /* TxD2 */
+ {0, 21, 1, 0, 1, -1}, /* TxD3 */
+ {0, 27, 1, 0, 1, -1}, /* TxER */
+ {0, 30, 1, 0, 1, -1}, /* TxEN */
+ {3, 23, 2, 0, 1, -1}, /* TxCLK->CLK3 */
+
+ {0, 22, 2, 0, 1, -1}, /* RxD0 */
+ {0, 23, 2, 0, 1, -1}, /* RxD1 */
+ {0, 24, 2, 0, 1, -1}, /* RxD2 */
+ {0, 25, 2, 0, 1, -1}, /* RxD3 */
+ {0, 26, 1, 0, 1, -1}, /* RxER */
+ {0, 28, 2, 0, 1, -1}, /* Rx_DV */
+ {3, 21, 2, 0, 1, -1}, /* RxCLK->CLK16 */
+ {0, 29, 2, 0, 1, -1}, /* COL */
+ {0, 31, 2, 0, 1, -1}, /* CRS */
- {3, 4, 3, 0, 2}, /* MDIO */
- {3, 5, 1, 0, 2}, /* MDC */
+ {3, 4, 3, 0, 2, -1}, /* MDIO */
+ {3, 5, 1, 0, 2, -1}, /* MDC */
- {0, 0, 0, 0, QE_IOP_TAB_END}, /* END of table */
+ {0, 0, 0, 0, QE_IOP_TAB_END, -1}, /* END of table */
};
int board_early_init_f(void)
--- a/board/freescale/mpc832xemds/mpc832xemds.c 2008-03-28
01:49:12.000000000 +0200
+++ b/board/freescale/mpc832xemds/mpc832xemds.c 2008-03-30
15:57:01.040395000 +0300
@@ -31,47 +31,47 @@
const qe_iop_conf_t qe_iop_conf_tab[] = {
/* ETH3 */
- {1, 0, 1, 0, 1}, /* TxD0 */
- {1, 1, 1, 0, 1}, /* TxD1 */
- {1, 2, 1, 0, 1}, /* TxD2 */
- {1, 3, 1, 0, 1}, /* TxD3 */
- {1, 9, 1, 0, 1}, /* TxER */
- {1, 12, 1, 0, 1}, /* TxEN */
- {3, 24, 2, 0, 1}, /* TxCLK->CLK10 */
-
- {1, 4, 2, 0, 1}, /* RxD0 */
- {1, 5, 2, 0, 1}, /* RxD1 */
- {1, 6, 2, 0, 1}, /* RxD2 */
- {1, 7, 2, 0, 1}, /* RxD3 */
- {1, 8, 2, 0, 1}, /* RxER */
- {1, 10, 2, 0, 1}, /* RxDV */
- {0, 13, 2, 0, 1}, /* RxCLK->CLK9 */
- {1, 11, 2, 0, 1}, /* COL */
- {1, 13, 2, 0, 1}, /* CRS */
+ {1, 0, 1, 0, 1, -1}, /* TxD0 */
+ {1, 1, 1, 0, 1, -1}, /* TxD1 */
+ {1, 2, 1, 0, 1, -1}, /* TxD2 */
+ {1, 3, 1, 0, 1, -1}, /* TxD3 */
+ {1, 9, 1, 0, 1, -1}, /* TxER */
+ {1, 12, 1, 0, 1, -1}, /* TxEN */
+ {3, 24, 2, 0, 1, -1}, /* TxCLK->CLK10 */
+
+ {1, 4, 2, 0, 1, -1}, /* RxD0 */
+ {1, 5, 2, 0, 1, -1}, /* RxD1 */
+ {1, 6, 2, 0, 1, -1}, /* RxD2 */
+ {1, 7, 2, 0, 1, -1}, /* RxD3 */
+ {1, 8, 2, 0, 1, -1}, /* RxER */
+ {1, 10, 2, 0, 1, -1}, /* RxDV */
+ {0, 13, 2, 0, 1, -1}, /* RxCLK->CLK9 */
+ {1, 11, 2, 0, 1, -1}, /* COL */
+ {1, 13, 2, 0, 1, -1}, /* CRS */
/* ETH4 */
- {1, 18, 1, 0, 1}, /* TxD0 */
- {1, 19, 1, 0, 1}, /* TxD1 */
- {1, 20, 1, 0, 1}, /* TxD2 */
- {1, 21, 1, 0, 1}, /* TxD3 */
- {1, 27, 1, 0, 1}, /* TxER */
- {1, 30, 1, 0, 1}, /* TxEN */
- {3, 6, 2, 0, 1}, /* TxCLK->CLK8 */
-
- {1, 22, 2, 0, 1}, /* RxD0 */
- {1, 23, 2, 0, 1}, /* RxD1 */
- {1, 24, 2, 0, 1}, /* RxD2 */
- {1, 25, 2, 0, 1}, /* RxD3 */
- {1, 26, 1, 0, 1}, /* RxER */
- {1, 28, 2, 0, 1}, /* Rx_DV */
- {3, 31, 2, 0, 1}, /* RxCLK->CLK7 */
- {1, 29, 2, 0, 1}, /* COL */
- {1, 31, 2, 0, 1}, /* CRS */
+ {1, 18, 1, 0, 1, -1}, /* TxD0 */
+ {1, 19, 1, 0, 1, -1}, /* TxD1 */
+ {1, 20, 1, 0, 1, -1}, /* TxD2 */
+ {1, 21, 1, 0, 1, -1}, /* TxD3 */
+ {1, 27, 1, 0, 1, -1}, /* TxER */
+ {1, 30, 1, 0, 1, -1}, /* TxEN */
+ {3, 6, 2, 0, 1, -1}, /* TxCLK->CLK8 */
+
+ {1, 22, 2, 0, 1, -1}, /* RxD0 */
+ {1, 23, 2, 0, 1, -1}, /* RxD1 */
+ {1, 24, 2, 0, 1, -1}, /* RxD2 */
+ {1, 25, 2, 0, 1, -1}, /* RxD3 */
+ {1, 26, 1, 0, 1, -1}, /* RxER */
+ {1, 28, 2, 0, 1, -1}, /* Rx_DV */
+ {3, 31, 2, 0, 1, -1}, /* RxCLK->CLK7 */
+ {1, 29, 2, 0, 1, -1}, /* COL */
+ {1, 31, 2, 0, 1, -1}, /* CRS */
- {3, 4, 3, 0, 2}, /* MDIO */
- {3, 5, 1, 0, 2}, /* MDC */
+ {3, 4, 3, 0, 2, -1}, /* MDIO */
+ {3, 5, 1, 0, 2, -1}, /* MDC */
- {0, 0, 0, 0, QE_IOP_TAB_END}, /* END of table */
+ {0, 0, 0, 0, QE_IOP_TAB_END, -1}, /* END of table */
};
int board_early_init_f(void)
--- a/board/freescale/mpc8360emds/mpc8360emds.c 2008-03-28
01:49:12.000000000 +0200
+++ b/board/freescale/mpc8360emds/mpc8360emds.c 2008-03-30
15:57:20.682650000 +0300
@@ -30,63 +30,63 @@
const qe_iop_conf_t qe_iop_conf_tab[] = {
/* GETH1 */
- {0, 3, 1, 0, 1}, /* TxD0 */
- {0, 4, 1, 0, 1}, /* TxD1 */
- {0, 5, 1, 0, 1}, /* TxD2 */
- {0, 6, 1, 0, 1}, /* TxD3 */
- {1, 6, 1, 0, 3}, /* TxD4 */
- {1, 7, 1, 0, 1}, /* TxD5 */
- {1, 9, 1, 0, 2}, /* TxD6 */
- {1, 10, 1, 0, 2}, /* TxD7 */
- {0, 9, 2, 0, 1}, /* RxD0 */
- {0, 10, 2, 0, 1}, /* RxD1 */
- {0, 11, 2, 0, 1}, /* RxD2 */
- {0, 12, 2, 0, 1}, /* RxD3 */
- {0, 13, 2, 0, 1}, /* RxD4 */
- {1, 1, 2, 0, 2}, /* RxD5 */
- {1, 0, 2, 0, 2}, /* RxD6 */
- {1, 4, 2, 0, 2}, /* RxD7 */
- {0, 7, 1, 0, 1}, /* TX_EN */
- {0, 8, 1, 0, 1}, /* TX_ER */
- {0, 15, 2, 0, 1}, /* RX_DV */
- {0, 16, 2, 0, 1}, /* RX_ER */
- {0, 0, 2, 0, 1}, /* RX_CLK */
- {2, 9, 1, 0, 3}, /* GTX_CLK - CLK10 */
- {2, 8, 2, 0, 1}, /* GTX125 - CLK9 */
+ {0, 3, 1, 0, 1, -1}, /* TxD0 */
+ {0, 4, 1, 0, 1, -1}, /* TxD1 */
+ {0, 5, 1, 0, 1, -1}, /* TxD2 */
+ {0, 6, 1, 0, 1, -1}, /* TxD3 */
+ {1, 6, 1, 0, 3, -1}, /* TxD4 */
+ {1, 7, 1, 0, 1, -1}, /* TxD5 */
+ {1, 9, 1, 0, 2, -1}, /* TxD6 */
+ {1, 10, 1, 0, 2, -1}, /* TxD7 */
+ {0, 9, 2, 0, 1, -1}, /* RxD0 */
+ {0, 10, 2, 0, 1, -1}, /* RxD1 */
+ {0, 11, 2, 0, 1, -1}, /* RxD2 */
+ {0, 12, 2, 0, 1, -1}, /* RxD3 */
+ {0, 13, 2, 0, 1, -1}, /* RxD4 */
+ {1, 1, 2, 0, 2, -1}, /* RxD5 */
+ {1, 0, 2, 0, 2, -1}, /* RxD6 */
+ {1, 4, 2, 0, 2, -1}, /* RxD7 */
+ {0, 7, 1, 0, 1, -1}, /* TX_EN */
+ {0, 8, 1, 0, 1, -1}, /* TX_ER */
+ {0, 15, 2, 0, 1, -1}, /* RX_DV */
+ {0, 16, 2, 0, 1, -1}, /* RX_ER */
+ {0, 0, 2, 0, 1, -1}, /* RX_CLK */
+ {2, 9, 1, 0, 3, -1}, /* GTX_CLK - CLK10 */
+ {2, 8, 2, 0, 1, -1}, /* GTX125 - CLK9 */
/* GETH2 */
- {0, 17, 1, 0, 1}, /* TxD0 */
- {0, 18, 1, 0, 1}, /* TxD1 */
- {0, 19, 1, 0, 1}, /* TxD2 */
- {0, 20, 1, 0, 1}, /* TxD3 */
- {1, 2, 1, 0, 1}, /* TxD4 */
- {1, 3, 1, 0, 2}, /* TxD5 */
- {1, 5, 1, 0, 3}, /* TxD6 */
- {1, 8, 1, 0, 3}, /* TxD7 */
- {0, 23, 2, 0, 1}, /* RxD0 */
- {0, 24, 2, 0, 1}, /* RxD1 */
- {0, 25, 2, 0, 1}, /* RxD2 */
- {0, 26, 2, 0, 1}, /* RxD3 */
- {0, 27, 2, 0, 1}, /* RxD4 */
- {1, 12, 2, 0, 2}, /* RxD5 */
- {1, 13, 2, 0, 3}, /* RxD6 */
- {1, 11, 2, 0, 2}, /* RxD7 */
- {0, 21, 1, 0, 1}, /* TX_EN */
- {0, 22, 1, 0, 1}, /* TX_ER */
- {0, 29, 2, 0, 1}, /* RX_DV */
- {0, 30, 2, 0, 1}, /* RX_ER */
- {0, 31, 2, 0, 1}, /* RX_CLK */
- {2, 2, 1, 0, 2}, /* GTX_CLK = CLK10 */
- {2, 3, 2, 0, 1}, /* GTX125 - CLK4 */
-
- {0, 1, 3, 0, 2}, /* MDIO */
- {0, 2, 1, 0, 1}, /* MDC */
-
- {5, 0, 1, 0, 2}, /* UART2_SOUT */
- {5, 1, 2, 0, 3}, /* UART2_CTS */
- {5, 2, 1, 0, 1}, /* UART2_RTS */
- {5, 3, 2, 0, 2}, /* UART2_SIN */
+ {0, 17, 1, 0, 1, -1}, /* TxD0 */
+ {0, 18, 1, 0, 1, -1}, /* TxD1 */
+ {0, 19, 1, 0, 1, -1}, /* TxD2 */
+ {0, 20, 1, 0, 1, -1}, /* TxD3 */
+ {1, 2, 1, 0, 1, -1}, /* TxD4 */
+ {1, 3, 1, 0, 2, -1}, /* TxD5 */
+ {1, 5, 1, 0, 3, -1}, /* TxD6 */
+ {1, 8, 1, 0, 3, -1}, /* TxD7 */
+ {0, 23, 2, 0, 1, -1}, /* RxD0 */
+ {0, 24, 2, 0, 1, -1}, /* RxD1 */
+ {0, 25, 2, 0, 1, -1}, /* RxD2 */
+ {0, 26, 2, 0, 1, -1}, /* RxD3 */
+ {0, 27, 2, 0, 1, -1}, /* RxD4 */
+ {1, 12, 2, 0, 2, -1}, /* RxD5 */
+ {1, 13, 2, 0, 3, -1}, /* RxD6 */
+ {1, 11, 2, 0, 2, -1}, /* RxD7 */
+ {0, 21, 1, 0, 1, -1}, /* TX_EN */
+ {0, 22, 1, 0, 1, -1}, /* TX_ER */
+ {0, 29, 2, 0, 1, -1}, /* RX_DV */
+ {0, 30, 2, 0, 1, -1}, /* RX_ER */
+ {0, 31, 2, 0, 1, -1}, /* RX_CLK */
+ {2, 2, 1, 0, 2, -1}, /* GTX_CLK = CLK10 */
+ {2, 3, 2, 0, 1, -1}, /* GTX125 - CLK4 */
+
+ {0, 1, 3, 0, 2, -1}, /* MDIO */
+ {0, 2, 1, 0, 1, -1}, /* MDC */
+
+ {5, 0, 1, 0, 2, -1}, /* UART2_SOUT */
+ {5, 1, 2, 0, 3, -1}, /* UART2_CTS */
+ {5, 2, 1, 0, 1, -1}, /* UART2_RTS */
+ {5, 3, 2, 0, 2, -1}, /* UART2_SIN */
- {0, 0, 0, 0, QE_IOP_TAB_END}, /* END of table */
+ {0, 0, 0, 0, QE_IOP_TAB_END, -1}, /* END of table */
};
int board_early_init_f(void)
--- a/board/freescale/mpc8360erdk/mpc8360erdk.c 2008-03-28
01:49:12.000000000 +0200
+++ b/board/freescale/mpc8360erdk/mpc8360erdk.c 2008-03-30
15:57:40.425878000 +0300
@@ -26,165 +26,165 @@
const qe_iop_conf_t qe_iop_conf_tab[] = {
/* MDIO */
- {0, 1, 3, 0, 2}, /* MDIO */
- {0, 2, 1, 0, 1}, /* MDC */
+ {0, 1, 3, 0, 2, -1}, /* MDIO */
+ {0, 2, 1, 0, 1, -1}, /* MDC */
/* UCC1 - UEC (Gigabit) */
- {0, 3, 1, 0, 1}, /* TxD0 */
- {0, 4, 1, 0, 1}, /* TxD1 */
- {0, 5, 1, 0, 1}, /* TxD2 */
- {0, 6, 1, 0, 1}, /* TxD3 */
- {0, 9, 2, 0, 1}, /* RxD0 */
- {0, 10, 2, 0, 1}, /* RxD1 */
- {0, 11, 2, 0, 1}, /* RxD2 */
- {0, 12, 2, 0, 1}, /* RxD3 */
- {0, 7, 1, 0, 1}, /* TX_EN */
- {0, 8, 1, 0, 1}, /* TX_ER */
- {0, 15, 2, 0, 1}, /* RX_DV */
- {0, 0, 2, 0, 1}, /* RX_CLK */
- {2, 9, 1, 0, 3}, /* GTX_CLK - CLK10 */
- {2, 8, 2, 0, 1}, /* GTX125 - CLK9 */
+ {0, 3, 1, 0, 1, -1}, /* TxD0 */
+ {0, 4, 1, 0, 1, -1}, /* TxD1 */
+ {0, 5, 1, 0, 1, -1}, /* TxD2 */
+ {0, 6, 1, 0, 1, -1}, /* TxD3 */
+ {0, 9, 2, 0, 1, -1}, /* RxD0 */
+ {0, 10, 2, 0, 1, -1}, /* RxD1 */
+ {0, 11, 2, 0, 1, -1}, /* RxD2 */
+ {0, 12, 2, 0, 1, -1}, /* RxD3 */
+ {0, 7, 1, 0, 1, -1}, /* TX_EN */
+ {0, 8, 1, 0, 1, -1}, /* TX_ER */
+ {0, 15, 2, 0, 1, -1}, /* RX_DV */
+ {0, 0, 2, 0, 1, -1}, /* RX_CLK */
+ {2, 9, 1, 0, 3, -1}, /* GTX_CLK - CLK10 */
+ {2, 8, 2, 0, 1, -1}, /* GTX125 - CLK9 */
/* UCC2 - UEC (Gigabit) */
- {0, 17, 1, 0, 1}, /* TxD0 */
- {0, 18, 1, 0, 1}, /* TxD1 */
- {0, 19, 1, 0, 1}, /* TxD2 */
- {0, 20, 1, 0, 1}, /* TxD3 */
- {0, 23, 2, 0, 1}, /* RxD0 */
- {0, 24, 2, 0, 1}, /* RxD1 */
- {0, 25, 2, 0, 1}, /* RxD2 */
- {0, 26, 2, 0, 1}, /* RxD3 */
- {0, 21, 1, 0, 1}, /* TX_EN */
- {0, 22, 1, 0, 1}, /* TX_ER */
- {0, 29, 2, 0, 1}, /* RX_DV */
- {0, 31, 2, 0, 1}, /* RX_CLK */
- {2, 2, 1, 0, 2}, /* GTX_CLK - CLK10 */
- {2, 3, 2, 0, 1}, /* GTX125 - CLK4 */
+ {0, 17, 1, 0, 1, -1}, /* TxD0 */
+ {0, 18, 1, 0, 1, -1}, /* TxD1 */
+ {0, 19, 1, 0, 1, -1}, /* TxD2 */
+ {0, 20, 1, 0, 1, -1}, /* TxD3 */
+ {0, 23, 2, 0, 1, -1}, /* RxD0 */
+ {0, 24, 2, 0, 1, -1}, /* RxD1 */
+ {0, 25, 2, 0, 1, -1}, /* RxD2 */
+ {0, 26, 2, 0, 1, -1}, /* RxD3 */
+ {0, 21, 1, 0, 1, -1}, /* TX_EN */
+ {0, 22, 1, 0, 1, -1}, /* TX_ER */
+ {0, 29, 2, 0, 1, -1}, /* RX_DV */
+ {0, 31, 2, 0, 1, -1}, /* RX_CLK */
+ {2, 2, 1, 0, 2, -1}, /* GTX_CLK - CLK10 */
+ {2, 3, 2, 0, 1, -1}, /* GTX125 - CLK4 */
/* UCC7 - UEC */
- {4, 0, 1, 0, 1}, /* TxD0 */
- {4, 1, 1, 0, 1}, /* TxD1 */
- {4, 2, 1, 0, 1}, /* TxD2 */
- {4, 3, 1, 0, 1}, /* TxD3 */
- {4, 6, 2, 0, 1}, /* RxD0 */
- {4, 7, 2, 0, 1}, /* RxD1 */
- {4, 8, 2, 0, 1}, /* RxD2 */
- {4, 9, 2, 0, 1}, /* RxD3 */
- {4, 4, 1, 0, 1}, /* TX_EN */
- {4, 5, 1, 0, 1}, /* TX_ER */
- {4, 12, 2, 0, 1}, /* RX_DV */
- {4, 13, 2, 0, 1}, /* RX_ER */
- {4, 10, 2, 0, 1}, /* COL */
- {4, 11, 2, 0, 1}, /* CRS */
- {2, 18, 2, 0, 1}, /* TX_CLK - CLK19 */
- {2, 19, 2, 0, 1}, /* RX_CLK - CLK20 */
+ {4, 0, 1, 0, 1, -1}, /* TxD0 */
+ {4, 1, 1, 0, 1, -1}, /* TxD1 */
+ {4, 2, 1, 0, 1, -1}, /* TxD2 */
+ {4, 3, 1, 0, 1, -1}, /* TxD3 */
+ {4, 6, 2, 0, 1, -1}, /* RxD0 */
+ {4, 7, 2, 0, 1, -1}, /* RxD1 */
+ {4, 8, 2, 0, 1, -1}, /* RxD2 */
+ {4, 9, 2, 0, 1, -1}, /* RxD3 */
+ {4, 4, 1, 0, 1, -1}, /* TX_EN */
+ {4, 5, 1, 0, 1, -1}, /* TX_ER */
+ {4, 12, 2, 0, 1, -1}, /* RX_DV */
+ {4, 13, 2, 0, 1, -1}, /* RX_ER */
+ {4, 10, 2, 0, 1, -1}, /* COL */
+ {4, 11, 2, 0, 1, -1}, /* CRS */
+ {2, 18, 2, 0, 1, -1}, /* TX_CLK - CLK19 */
+ {2, 19, 2, 0, 1, -1}, /* RX_CLK - CLK20 */
/* UCC4 - UEC */
- {1, 14, 1, 0, 1}, /* TxD0 */
- {1, 15, 1, 0, 1}, /* TxD1 */
- {1, 16, 1, 0, 1}, /* TxD2 */
- {1, 17, 1, 0, 1}, /* TxD3 */
- {1, 20, 2, 0, 1}, /* RxD0 */
- {1, 21, 2, 0, 1}, /* RxD1 */
- {1, 22, 2, 0, 1}, /* RxD2 */
- {1, 23, 2, 0, 1}, /* RxD3 */
- {1, 18, 1, 0, 1}, /* TX_EN */
- {1, 19, 1, 0, 2}, /* TX_ER */
- {1, 26, 2, 0, 1}, /* RX_DV */
- {1, 27, 2, 0, 1}, /* RX_ER */
- {1, 24, 2, 0, 1}, /* COL */
- {1, 25, 2, 0, 1}, /* CRS */
- {2, 6, 2, 0, 1}, /* TX_CLK - CLK7 */
- {2, 7, 2, 0, 1}, /* RX_CLK - CLK8 */
+ {1, 14, 1, 0, 1, -1}, /* TxD0 */
+ {1, 15, 1, 0, 1, -1}, /* TxD1 */
+ {1, 16, 1, 0, 1, -1}, /* TxD2 */
+ {1, 17, 1, 0, 1, -1}, /* TxD3 */
+ {1, 20, 2, 0, 1, -1}, /* RxD0 */
+ {1, 21, 2, 0, 1, -1}, /* RxD1 */
+ {1, 22, 2, 0, 1, -1}, /* RxD2 */
+ {1, 23, 2, 0, 1, -1}, /* RxD3 */
+ {1, 18, 1, 0, 1, -1}, /* TX_EN */
+ {1, 19, 1, 0, 2, -1}, /* TX_ER */
+ {1, 26, 2, 0, 1, -1}, /* RX_DV */
+ {1, 27, 2, 0, 1, -1}, /* RX_ER */
+ {1, 24, 2, 0, 1, -1}, /* COL */
+ {1, 25, 2, 0, 1, -1}, /* CRS */
+ {2, 6, 2, 0, 1, -1}, /* TX_CLK - CLK7 */
+ {2, 7, 2, 0, 1, -1}, /* RX_CLK - CLK8 */
/* PCI1 */
- {5, 4, 2, 0, 3}, /* PCI_M66EN */
- {5, 5, 1, 0, 3}, /* PCI_INTA */
- {5, 6, 1, 0, 3}, /* PCI_RSTO */
- {5, 7, 3, 0, 3}, /* PCI_C_BE0 */
- {5, 8, 3, 0, 3}, /* PCI_C_BE1 */
- {5, 9, 3, 0, 3}, /* PCI_C_BE2 */
- {5, 10, 3, 0, 3}, /* PCI_C_BE3 */
- {5, 11, 3, 0, 3}, /* PCI_PAR */
- {5, 12, 3, 0, 3}, /* PCI_FRAME */
- {5, 13, 3, 0, 3}, /* PCI_TRDY */
- {5, 14, 3, 0, 3}, /* PCI_IRDY */
- {5, 15, 3, 0, 3}, /* PCI_STOP */
- {5, 16, 3, 0, 3}, /* PCI_DEVSEL */
- {5, 17, 0, 0, 0}, /* PCI_IDSEL */
- {5, 18, 3, 0, 3}, /* PCI_SERR */
- {5, 19, 3, 0, 3}, /* PCI_PERR */
- {5, 20, 3, 0, 3}, /* PCI_REQ0 */
- {5, 21, 2, 0, 3}, /* PCI_REQ1 */
- {5, 22, 2, 0, 3}, /* PCI_GNT2 */
- {5, 23, 3, 0, 3}, /* PCI_GNT0 */
- {5, 24, 1, 0, 3}, /* PCI_GNT1 */
- {5, 25, 1, 0, 3}, /* PCI_GNT2 */
- {5, 26, 0, 0, 0}, /* PCI_CLK0 */
- {5, 27, 0, 0, 0}, /* PCI_CLK1 */
- {5, 28, 0, 0, 0}, /* PCI_CLK2 */
- {5, 29, 0, 0, 3}, /* PCI_SYNC_OUT */
- {6, 0, 3, 0, 3}, /* PCI_AD0 */
- {6, 1, 3, 0, 3}, /* PCI_AD1 */
- {6, 2, 3, 0, 3}, /* PCI_AD2 */
- {6, 3, 3, 0, 3}, /* PCI_AD3 */
- {6, 4, 3, 0, 3}, /* PCI_AD4 */
- {6, 5, 3, 0, 3}, /* PCI_AD5 */
- {6, 6, 3, 0, 3}, /* PCI_AD6 */
- {6, 7, 3, 0, 3}, /* PCI_AD7 */
- {6, 8, 3, 0, 3}, /* PCI_AD8 */
- {6, 9, 3, 0, 3}, /* PCI_AD9 */
- {6, 10, 3, 0, 3}, /* PCI_AD10 */
- {6, 11, 3, 0, 3}, /* PCI_AD11 */
- {6, 12, 3, 0, 3}, /* PCI_AD12 */
- {6, 13, 3, 0, 3}, /* PCI_AD13 */
- {6, 14, 3, 0, 3}, /* PCI_AD14 */
- {6, 15, 3, 0, 3}, /* PCI_AD15 */
- {6, 16, 3, 0, 3}, /* PCI_AD16 */
- {6, 17, 3, 0, 3}, /* PCI_AD17 */
- {6, 18, 3, 0, 3}, /* PCI_AD18 */
- {6, 19, 3, 0, 3}, /* PCI_AD19 */
- {6, 20, 3, 0, 3}, /* PCI_AD20 */
- {6, 21, 3, 0, 3}, /* PCI_AD21 */
- {6, 22, 3, 0, 3}, /* PCI_AD22 */
- {6, 23, 3, 0, 3}, /* PCI_AD23 */
- {6, 24, 3, 0, 3}, /* PCI_AD24 */
- {6, 25, 3, 0, 3}, /* PCI_AD25 */
- {6, 26, 3, 0, 3}, /* PCI_AD26 */
- {6, 27, 3, 0, 3}, /* PCI_AD27 */
- {6, 28, 3, 0, 3}, /* PCI_AD28 */
- {6, 29, 3, 0, 3}, /* PCI_AD29 */
- {6, 30, 3, 0, 3}, /* PCI_AD30 */
- {6, 31, 3, 0, 3}, /* PCI_AD31 */
+ {5, 4, 2, 0, 3, -1}, /* PCI_M66EN */
+ {5, 5, 1, 0, 3, -1}, /* PCI_INTA */
+ {5, 6, 1, 0, 3, -1}, /* PCI_RSTO */
+ {5, 7, 3, 0, 3, -1}, /* PCI_C_BE0 */
+ {5, 8, 3, 0, 3, -1}, /* PCI_C_BE1 */
+ {5, 9, 3, 0, 3, -1}, /* PCI_C_BE2 */
+ {5, 10, 3, 0, 3, -1}, /* PCI_C_BE3 */
+ {5, 11, 3, 0, 3, -1}, /* PCI_PAR */
+ {5, 12, 3, 0, 3, -1}, /* PCI_FRAME */
+ {5, 13, 3, 0, 3, -1}, /* PCI_TRDY */
+ {5, 14, 3, 0, 3, -1}, /* PCI_IRDY */
+ {5, 15, 3, 0, 3, -1}, /* PCI_STOP */
+ {5, 16, 3, 0, 3, -1}, /* PCI_DEVSEL */
+ {5, 17, 0, 0, 0, -1}, /* PCI_IDSEL */
+ {5, 18, 3, 0, 3, -1}, /* PCI_SERR */
+ {5, 19, 3, 0, 3, -1}, /* PCI_PERR */
+ {5, 20, 3, 0, 3, -1}, /* PCI_REQ0 */
+ {5, 21, 2, 0, 3, -1}, /* PCI_REQ1 */
+ {5, 22, 2, 0, 3, -1}, /* PCI_GNT2 */
+ {5, 23, 3, 0, 3, -1}, /* PCI_GNT0 */
+ {5, 24, 1, 0, 3, -1}, /* PCI_GNT1 */
+ {5, 25, 1, 0, 3, -1}, /* PCI_GNT2 */
+ {5, 26, 0, 0, 0, -1}, /* PCI_CLK0 */
+ {5, 27, 0, 0, 0, -1}, /* PCI_CLK1 */
+ {5, 28, 0, 0, 0, -1}, /* PCI_CLK2 */
+ {5, 29, 0, 0, 3, -1}, /* PCI_SYNC_OUT */
+ {6, 0, 3, 0, 3, -1}, /* PCI_AD0 */
+ {6, 1, 3, 0, 3, -1}, /* PCI_AD1 */
+ {6, 2, 3, 0, 3, -1}, /* PCI_AD2 */
+ {6, 3, 3, 0, 3, -1}, /* PCI_AD3 */
+ {6, 4, 3, 0, 3, -1}, /* PCI_AD4 */
+ {6, 5, 3, 0, 3, -1}, /* PCI_AD5 */
+ {6, 6, 3, 0, 3, -1}, /* PCI_AD6 */
+ {6, 7, 3, 0, 3, -1}, /* PCI_AD7 */
+ {6, 8, 3, 0, 3, -1}, /* PCI_AD8 */
+ {6, 9, 3, 0, 3, -1}, /* PCI_AD9 */
+ {6, 10, 3, 0, 3, -1}, /* PCI_AD10 */
+ {6, 11, 3, 0, 3, -1}, /* PCI_AD11 */
+ {6, 12, 3, 0, 3, -1}, /* PCI_AD12 */
+ {6, 13, 3, 0, 3, -1}, /* PCI_AD13 */
+ {6, 14, 3, 0, 3, -1}, /* PCI_AD14 */
+ {6, 15, 3, 0, 3, -1}, /* PCI_AD15 */
+ {6, 16, 3, 0, 3, -1}, /* PCI_AD16 */
+ {6, 17, 3, 0, 3, -1}, /* PCI_AD17 */
+ {6, 18, 3, 0, 3, -1}, /* PCI_AD18 */
+ {6, 19, 3, 0, 3, -1}, /* PCI_AD19 */
+ {6, 20, 3, 0, 3, -1}, /* PCI_AD20 */
+ {6, 21, 3, 0, 3, -1}, /* PCI_AD21 */
+ {6, 22, 3, 0, 3, -1}, /* PCI_AD22 */
+ {6, 23, 3, 0, 3, -1}, /* PCI_AD23 */
+ {6, 24, 3, 0, 3, -1}, /* PCI_AD24 */
+ {6, 25, 3, 0, 3, -1}, /* PCI_AD25 */
+ {6, 26, 3, 0, 3, -1}, /* PCI_AD26 */
+ {6, 27, 3, 0, 3, -1}, /* PCI_AD27 */
+ {6, 28, 3, 0, 3, -1}, /* PCI_AD28 */
+ {6, 29, 3, 0, 3, -1}, /* PCI_AD29 */
+ {6, 30, 3, 0, 3, -1}, /* PCI_AD30 */
+ {6, 31, 3, 0, 3, -1}, /* PCI_AD31 */
/* NAND */
- {4, 18, 2, 0, 0}, /* NAND_RYnBY */
+ {4, 18, 2, 0, 0, -1}, /* NAND_RYnBY */
/* DUART - UART2 */
- {5, 0, 1, 0, 2}, /* UART2_SOUT */
- {5, 2, 1, 0, 1}, /* UART2_RTS */
- {5, 3, 2, 0, 2}, /* UART2_SIN */
- {5, 1, 2, 0, 3}, /* UART2_CTS */
+ {5, 0, 1, 0, 2, -1}, /* UART2_SOUT */
+ {5, 2, 1, 0, 1, -1}, /* UART2_RTS */
+ {5, 3, 2, 0, 2, -1}, /* UART2_SIN */
+ {5, 1, 2, 0, 3, -1}, /* UART2_CTS */
/* UCC5 - UART3 */
- {3, 0, 1, 0, 1}, /* UART3_TX */
- {3, 4, 1, 0, 1}, /* UART3_RTS */
- {3, 6, 2, 0, 1}, /* UART3_RX */
- {3, 12, 2, 0, 0}, /* UART3_CTS */
- {3, 13, 2, 0, 0}, /* UCC5_CD */
+ {3, 0, 1, 0, 1, -1}, /* UART3_TX */
+ {3, 4, 1, 0, 1, -1}, /* UART3_RTS */
+ {3, 6, 2, 0, 1, -1}, /* UART3_RX */
+ {3, 12, 2, 0, 0, -1}, /* UART3_CTS */
+ {3, 13, 2, 0, 0, -1}, /* UCC5_CD */
/* UCC6 - UART4 */
- {3, 14, 1, 0, 1}, /* UART4_TX */
- {3, 18, 1, 0, 1}, /* UART4_RTS */
- {3, 20, 2, 0, 1}, /* UART4_RX */
- {3, 26, 2, 0, 0}, /* UART4_CTS */
- {3, 27, 2, 0, 0}, /* UCC6_CD */
+ {3, 14, 1, 0, 1, -1}, /* UART4_TX */
+ {3, 18, 1, 0, 1, -1}, /* UART4_RTS */
+ {3, 20, 2, 0, 1, -1}, /* UART4_RX */
+ {3, 26, 2, 0, 0, -1}, /* UART4_CTS */
+ {3, 27, 2, 0, 0, -1}, /* UCC6_CD */
/* Fujitsu MB86277 (MINT) graphics controller */
- {0, 30, 1, 0, 0}, /* nSRESET_GRAPHICS */
- {1, 5, 1, 0, 0}, /* nXRST_GRAPHICS */
- {1, 7, 1, 0, 0}, /* LVDS_BKLT_CTR */
- {2, 16, 1, 0, 0}, /* LVDS_BKLT_EN */
+ {0, 30, 1, 0, 0, -1}, /* nSRESET_GRAPHICS */
+ {1, 5, 1, 0, 0, -1}, /* nXRST_GRAPHICS */
+ {1, 7, 1, 0, 0, -1}, /* LVDS_BKLT_CTR */
+ {2, 16, 1, 0, 0, -1}, /* LVDS_BKLT_EN */
/* AD7843 ADC/Touchscreen controller */
{4, 14, 1, 0, 0}, /* SPI_nCS0 */
@@ -204,7 +204,7 @@ const qe_iop_conf_t qe_iop_conf_tab[] =
{4, 21, 1, 0, 0}, /* SUSPND */
/* END of table */
- {0, 0, 0, 0, QE_IOP_TAB_END},
+ {0, 0, 0, 0, QE_IOP_TAB_END, -1},
};
int board_early_init_f(void)
--- a/board/freescale/mpc8568mds/mpc8568mds.c 2008-03-28
01:49:12.000000000 +0200
+++ b/board/freescale/mpc8568mds/mpc8568mds.c 2008-03-30
15:57:57.592361000 +0300
@@ -37,64 +37,64 @@
const qe_iop_conf_t qe_iop_conf_tab[] = {
/* GETH1 */
- {4, 10, 1, 0, 2}, /* TxD0 */
- {4, 9, 1, 0, 2}, /* TxD1 */
- {4, 8, 1, 0, 2}, /* TxD2 */
- {4, 7, 1, 0, 2}, /* TxD3 */
- {4, 23, 1, 0, 2}, /* TxD4 */
- {4, 22, 1, 0, 2}, /* TxD5 */
- {4, 21, 1, 0, 2}, /* TxD6 */
- {4, 20, 1, 0, 2}, /* TxD7 */
- {4, 15, 2, 0, 2}, /* RxD0 */
- {4, 14, 2, 0, 2}, /* RxD1 */
- {4, 13, 2, 0, 2}, /* RxD2 */
- {4, 12, 2, 0, 2}, /* RxD3 */
- {4, 29, 2, 0, 2}, /* RxD4 */
- {4, 28, 2, 0, 2}, /* RxD5 */
- {4, 27, 2, 0, 2}, /* RxD6 */
- {4, 26, 2, 0, 2}, /* RxD7 */
- {4, 11, 1, 0, 2}, /* TX_EN */
- {4, 24, 1, 0, 2}, /* TX_ER */
- {4, 16, 2, 0, 2}, /* RX_DV */
- {4, 30, 2, 0, 2}, /* RX_ER */
- {4, 17, 2, 0, 2}, /* RX_CLK */
- {4, 19, 1, 0, 2}, /* GTX_CLK */
- {1, 31, 2, 0, 3}, /* GTX125 */
+ {4, 10, 1, 0, 2, -1}, /* TxD0 */
+ {4, 9, 1, 0, 2, -1}, /* TxD1 */
+ {4, 8, 1, 0, 2, -1}, /* TxD2 */
+ {4, 7, 1, 0, 2, -1}, /* TxD3 */
+ {4, 23, 1, 0, 2, -1}, /* TxD4 */
+ {4, 22, 1, 0, 2, -1}, /* TxD5 */
+ {4, 21, 1, 0, 2, -1}, /* TxD6 */
+ {4, 20, 1, 0, 2, -1}, /* TxD7 */
+ {4, 15, 2, 0, 2, -1}, /* RxD0 */
+ {4, 14, 2, 0, 2, -1}, /* RxD1 */
+ {4, 13, 2, 0, 2, -1}, /* RxD2 */
+ {4, 12, 2, 0, 2, -1}, /* RxD3 */
+ {4, 29, 2, 0, 2, -1}, /* RxD4 */
+ {4, 28, 2, 0, 2, -1}, /* RxD5 */
+ {4, 27, 2, 0, 2, -1}, /* RxD6 */
+ {4, 26, 2, 0, 2, -1}, /* RxD7 */
+ {4, 11, 1, 0, 2, -1}, /* TX_EN */
+ {4, 24, 1, 0, 2, -1}, /* TX_ER */
+ {4, 16, 2, 0, 2, -1}, /* RX_DV */
+ {4, 30, 2, 0, 2, -1}, /* RX_ER */
+ {4, 17, 2, 0, 2, -1}, /* RX_CLK */
+ {4, 19, 1, 0, 2, -1}, /* GTX_CLK */
+ {1, 31, 2, 0, 3, -1}, /* GTX125 */
/* GETH2 */
- {5, 10, 1, 0, 2}, /* TxD0 */
- {5, 9, 1, 0, 2}, /* TxD1 */
- {5, 8, 1, 0, 2}, /* TxD2 */
- {5, 7, 1, 0, 2}, /* TxD3 */
- {5, 23, 1, 0, 2}, /* TxD4 */
- {5, 22, 1, 0, 2}, /* TxD5 */
- {5, 21, 1, 0, 2}, /* TxD6 */
- {5, 20, 1, 0, 2}, /* TxD7 */
- {5, 15, 2, 0, 2}, /* RxD0 */
- {5, 14, 2, 0, 2}, /* RxD1 */
- {5, 13, 2, 0, 2}, /* RxD2 */
- {5, 12, 2, 0, 2}, /* RxD3 */
- {5, 29, 2, 0, 2}, /* RxD4 */
- {5, 28, 2, 0, 2}, /* RxD5 */
- {5, 27, 2, 0, 3}, /* RxD6 */
- {5, 26, 2, 0, 2}, /* RxD7 */
- {5, 11, 1, 0, 2}, /* TX_EN */
- {5, 24, 1, 0, 2}, /* TX_ER */
- {5, 16, 2, 0, 2}, /* RX_DV */
- {5, 30, 2, 0, 2}, /* RX_ER */
- {5, 17, 2, 0, 2}, /* RX_CLK */
- {5, 19, 1, 0, 2}, /* GTX_CLK */
- {1, 31, 2, 0, 3}, /* GTX125 */
- {4, 6, 3, 0, 2}, /* MDIO */
- {4, 5, 1, 0, 2}, /* MDC */
+ {5, 10, 1, 0, 2, -1}, /* TxD0 */
+ {5, 9, 1, 0, 2, -1}, /* TxD1 */
+ {5, 8, 1, 0, 2, -1}, /* TxD2 */
+ {5, 7, 1, 0, 2, -1}, /* TxD3 */
+ {5, 23, 1, 0, 2, -1}, /* TxD4 */
+ {5, 22, 1, 0, 2, -1}, /* TxD5 */
+ {5, 21, 1, 0, 2, -1}, /* TxD6 */
+ {5, 20, 1, 0, 2, -1}, /* TxD7 */
+ {5, 15, 2, 0, 2, -1}, /* RxD0 */
+ {5, 14, 2, 0, 2, -1}, /* RxD1 */
+ {5, 13, 2, 0, 2, -1}, /* RxD2 */
+ {5, 12, 2, 0, 2, -1}, /* RxD3 */
+ {5, 29, 2, 0, 2, -1}, /* RxD4 */
+ {5, 28, 2, 0, 2, -1}, /* RxD5 */
+ {5, 27, 2, 0, 3, -1}, /* RxD6 */
+ {5, 26, 2, 0, 2, -1}, /* RxD7 */
+ {5, 11, 1, 0, 2, -1}, /* TX_EN */
+ {5, 24, 1, 0, 2, -1}, /* TX_ER */
+ {5, 16, 2, 0, 2, -1}, /* RX_DV */
+ {5, 30, 2, 0, 2, -1}, /* RX_ER */
+ {5, 17, 2, 0, 2, -1}, /* RX_CLK */
+ {5, 19, 1, 0, 2, -1}, /* GTX_CLK */
+ {1, 31, 2, 0, 3, -1}, /* GTX125 */
+ {4, 6, 3, 0, 2, -1}, /* MDIO */
+ {4, 5, 1, 0, 2, -1}, /* MDC */
/* UART1 */
- {2, 0, 1, 0, 2}, /* UART_SOUT1 */
- {2, 1, 1, 0, 2}, /* UART_RTS1 */
- {2, 2, 2, 0, 2}, /* UART_CTS1 */
- {2, 3, 2, 0, 2}, /* UART_SIN1 */
+ {2, 0, 1, 0, 2, -1}, /* UART_SOUT1 */
+ {2, 1, 1, 0, 2, -1}, /* UART_RTS1 */
+ {2, 2, 2, 0, 2, -1}, /* UART_CTS1 */
+ {2, 3, 2, 0, 2, -1}, /* UART_SIN1 */
- {0, 0, 0, 0, QE_IOP_TAB_END}, /* END of table */
+ {0, 0, 0, 0, QE_IOP_TAB_END, -1}, /* END of table */
};
-------------------------------------------------------------------------
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