In message <[EMAIL PROTECTED]> you wrote:
>
> The 7610 and related parts have an L2IP bit in the L2CR that is
> monitored to signal when the L2 cache invalidate is complete whereas the
> 7450 and related parts utilize L2I for this purpose. However, the
> current code does not account for this difference. Additionally the 86xx
> L2 cache invalidate code used an "andi" instruction where an "andis"
> instruction should have been used.
>
> This patch addresses both of these bugs.
>
>
> Signed-off-by: Travis Wheatley <[EMAIL PROTECTED]>
> ---
> cpu/74xx_7xx/cache.S | 21 ++++++++++++++++++++-
> cpu/mpc86xx/cache.S | 2 +-
> 2 files changed, 21 insertions(+), 2 deletions(-)
Applied, thanks.
Best regards,
Wolfgang Denk
--
DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: [EMAIL PROTECTED]
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