On Sat, Sep 27, 2008 at 1:40 AM, Jason Jin <[EMAIL PROTECTED]> wrote: > On 8536DS board, When the DDR clk is set async mode(SW3[6:8] != 111), > The display is still sync mode DDR freq. This patch try to fix > this. The display DDR freq is now the actual freq in both > sync and async mode. > > Signed-off-by: Jason Jin <[EMAIL PROTECTED]>
Applied, thanks _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
