Signed-off-by: Stefan Roese <[EMAIL PROTECTED]>
---
include/configs/neo.h | 86 ++++++++++++++++++++++++------------------------
1 files changed, 43 insertions(+), 43 deletions(-)
diff --git a/include/configs/neo.h b/include/configs/neo.h
index a150cdd..f275c7b 100644
--- a/include/configs/neo.h
+++ b/include/configs/neo.h
@@ -83,34 +83,34 @@
#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */
/* SDRAM timings used in datasheet */
-#define CFG_SDRAM_CL 3 /* CAS latency */
-#define CFG_SDRAM_tRP 20 /* PRECHARGE command period */
-#define CFG_SDRAM_tRC 66 /* ACTIVE-to-ACTIVE command period */
-#define CFG_SDRAM_tRCD 20 /* ACTIVE-to-READ delay */
-#define CFG_SDRAM_tRFC 66 /* Auto refresh period */
+#define CONFIG_SYS_SDRAM_CL 3 /* CAS latency */
+#define CONFIG_SYS_SDRAM_tRP 20 /* PRECHARGE command period */
+#define CONFIG_SYS_SDRAM_tRC 66 /* ACTIVE-to-ACTIVE command
period */
+#define CONFIG_SYS_SDRAM_tRCD 20 /* ACTIVE-to-READ delay */
+#define CONFIG_SYS_SDRAM_tRFC 66 /* Auto refresh period */
/*
- * If CFG_EXT_SERIAL_CLOCK, then the UART divisor is 1.
- * If CFG_405_UART_ERRATA_59, then UART divisor is 31.
- * Otherwise, UART divisor is determined by CPU Clock and CFG_BASE_BAUD value.
+ * If CONFIG_SYS_EXT_SERIAL_CLOCK, then the UART divisor is 1.
+ * If CONFIG_SYS_405_UART_ERRATA_59, then UART divisor is 31.
+ * Otherwise, UART divisor is determined by CPU Clock and CONFIG_SYS_BASE_BAUD
value.
* The Linux BASE_BAUD define should match this configuration.
* baseBaud = cpuClock/(uartDivisor*16)
- * If CFG_405_UART_ERRATA_59 and 200MHz CPU clock,
+ * If CONFIG_SYS_405_UART_ERRATA_59 and 200MHz CPU clock,
* set Linux BASE_BAUD to 403200.
*/
#undef CONFIG_SERIAL_SOFTWARE_FIFO
-#undef CFG_EXT_SERIAL_CLOCK /* external serial clock */
-#undef CFG_405_UART_ERRATA_59 /* 405GP/CR Rev. D silicon */
-#define CFG_BASE_BAUD 691200
+#undef CONFIG_SYS_EXT_SERIAL_CLOCK /* external serial clock */
+#undef CONFIG_SYS_405_UART_ERRATA_59 /* 405GP/CR Rev. D silicon */
+#define CONFIG_SYS_BASE_BAUD 691200
/*
* I2C stuff
*/
-#define CFG_I2C_SPEED 100000 /* I2C speed and slave address */
+#define CONFIG_SYS_I2C_SPEED 100000 /* I2C speed and slave address
*/
/* RTC */
#define CONFIG_RTC_DS1337
-#define CFG_I2C_RTC_ADDR 0x68
+#define CONFIG_SYS_I2C_RTC_ADDR 0x68
/* Temp sensor/hwmon/dtt */
#define CONFIG_DTT_LM63 1 /* National LM63 */
@@ -122,27 +122,27 @@
/*
* FLASH organization
*/
-#define CFG_FLASH_CFI /* The flash is CFI compatible
*/
+#define CONFIG_SYS_FLASH_CFI /* The flash is CFI
compatible */
#define CONFIG_FLASH_CFI_DRIVER /* Use common CFI
driver */
-#define CFG_FLASH_BASE 0xFC000000
-#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE }
+#define CONFIG_SYS_FLASH_BASE 0xFC000000
+#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
-#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks
*/
-#define CFG_MAX_FLASH_SECT 512 /* max number of sectors on one chip
*/
+#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks
*/
+#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max number of sectors on one
chip */
-#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms)
*/
-#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms)
*/
+#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in
ms) */
+#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in
ms) */
-#define CFG_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster)
*/
-#define CFG_FLASH_PROTECTION 1 /* use hardware flash protection
*/
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x
faster) */
+#define CONFIG_SYS_FLASH_PROTECTION 1 /* use hardware flash
protection */
-#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo
*/
-#define CFG_FLASH_QUIET_TEST 1 /* don't warn upon unknown flash
*/
+#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector
on flinfo */
+#define CONFIG_SYS_FLASH_QUIET_TEST 1 /* don't warn upon unknown
flash */
#ifdef CONFIG_ENV_IS_IN_FLASH
#define CONFIG_ENV_SECT_SIZE 0x20000 /* size of one complete sector
*/
-#define CONFIG_ENV_ADDR
((-CFG_MONITOR_LEN)-CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_ADDR
((-CONFIG_SYS_MONITOR_LEN)-CONFIG_ENV_SECT_SIZE)
#define CONFIG_ENV_SIZE 0x2000 /* Total Size of Environment
Sector */
/* Address and size of Redundant Environment Sector */
@@ -153,7 +153,7 @@
/*
* PPC405 GPIO Configuration
*/
-#define CFG_4xx_GPIO_TABLE { /* GPIO
Alternate1 */ \
+#define CONFIG_SYS_4xx_GPIO_TABLE { /* GPIO
Alternate1 */ \
{
\
/* GPIO Core 0 */
\
{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO0 PerBLast
*/ \
@@ -195,37 +195,37 @@
* Definitions for initial stack pointer and data area (in data cache)
*/
/* use on chip memory (OCM) for temperary stack until sdram is tested */
-#define CFG_TEMP_STACK_OCM 1
+#define CONFIG_SYS_TEMP_STACK_OCM 1
/* On Chip Memory location */
-#define CFG_OCM_DATA_ADDR 0xF8000000
-#define CFG_OCM_DATA_SIZE 0x1000
-#define CFG_INIT_RAM_ADDR CFG_OCM_DATA_ADDR /* inside of SDRAM
*/
-#define CFG_INIT_RAM_END CFG_OCM_DATA_SIZE /* End of used area in RAM
*/
+#define CONFIG_SYS_OCM_DATA_ADDR 0xF8000000
+#define CONFIG_SYS_OCM_DATA_SIZE 0x1000
+#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR /* inside of
SDRAM */
+#define CONFIG_SYS_INIT_RAM_END CONFIG_SYS_OCM_DATA_SIZE /* End of used
area in RAM */
-#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data
*/
-#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
+#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for
initial data */
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END -
CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
/*
* External Bus Controller (EBC) Setup
*/
/* Memory Bank 0 (NOR-FLASH) initialization */
-#define CFG_EBC_PB0AP 0x92015480
-#define CFG_EBC_PB0CR 0xFC0DA000 /*
BAS=0xFC0,BS=64MB,BU=R/W,BW=16bit */
+#define CONFIG_SYS_EBC_PB0AP 0x92015480
+#define CONFIG_SYS_EBC_PB0CR 0xFC0DA000 /*
BAS=0xFC0,BS=64MB,BU=R/W,BW=16bit */
/* Memory Bank 1 (NVRAM) initialization
*/
-#define CFG_EBC_PB1AP 0x92015480
-#define CFG_EBC_PB1CR 0xFB85A000 /* BAS=0xFF8,BS=4MB,BU=R/W,BW=8bit
*/
+#define CONFIG_SYS_EBC_PB1AP 0x92015480
+#define CONFIG_SYS_EBC_PB1CR 0xFB85A000 /*
BAS=0xFF8,BS=4MB,BU=R/W,BW=8bit */
/* Memory Bank 2 (FPGA) initialization */
#define CONFIG_FPGA_BASE 0x7f100000
-#define CFG_EBC_PB2AP 0x92015480
-#define CFG_EBC_PB2CR 0x7f11a000 /* BAS=0x7f1,BS=1MB,BU=R/W,BW=16bit
*/
+#define CONFIG_SYS_EBC_PB2AP 0x92015480
+#define CONFIG_SYS_EBC_PB2CR 0x7f11a000 /*
BAS=0x7f1,BS=1MB,BU=R/W,BW=16bit */
/* Memory Bank 3 (Latches) initialization */
-#define CFG_EBC_PB3AP 0x92015480
-#define CFG_EBC_PB3CR 0x7f21a000 /* BAS=0x7f2,BS=1MB,BU=R/W,BW=16bit
*/
+#define CONFIG_SYS_EBC_PB3AP 0x92015480
+#define CONFIG_SYS_EBC_PB3CR 0x7f21a000 /*
BAS=0x7f2,BS=1MB,BU=R/W,BW=16bit */
#endif /* __CONFIG_H */
--
1.6.0.2
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