From: TsiChung Liew <[EMAIL PROTECTED]>
Consolidate FlexCan and PWM structures and
definitions in immap_5xxx.h and m5xxx.h to more
unify modules header files
Signed-off-by: TsiChung Liew <[EMAIL PROTECTED]>
---
include/asm-m68k/coldfire/flexcan.h | 219 +++++++++++++++++++++++++++++++++++
include/asm-m68k/coldfire/pwm.h | 115 ++++++++++++++++++
include/asm-m68k/immap_5227x.h | 8 ++
include/asm-m68k/immap_5235.h | 24 +---
include/asm-m68k/immap_5253.h | 11 ++-
include/asm-m68k/immap_5272.h | 18 +---
include/asm-m68k/immap_5275.h | 18 +---
include/asm-m68k/immap_5282.h | 5 +
include/asm-m68k/immap_5329.h | 64 +---------
include/asm-m68k/immap_547x_8x.h | 6 +
include/asm-m68k/m5235.h | 93 ---------------
include/asm-m68k/m5329.h | 142 ----------------------
12 files changed, 375 insertions(+), 348 deletions(-)
create mode 100644 include/asm-m68k/coldfire/flexcan.h
create mode 100644 include/asm-m68k/coldfire/pwm.h
diff --git a/include/asm-m68k/coldfire/flexcan.h
b/include/asm-m68k/coldfire/flexcan.h
new file mode 100644
index 0000000..cafd44f
--- /dev/null
+++ b/include/asm-m68k/coldfire/flexcan.h
@@ -0,0 +1,219 @@
+/*
+ * Flex CAN Memory Map
+ *
+ * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
+ * TsiChung Liew ([EMAIL PROTECTED])
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __FLEXCAN_H__
+#define __FLEXCAN_H__
+
+/* FlexCan Message Buffer */
+typedef struct can_msgbuf_ctrl {
+#ifdef CONFIG_M5282
+ u8 tmstamp; /* 0x00 Timestamp */
+ u8 ctrl; /* 0x01 Control */
+ u16 idh; /* 0x02 ID High */
+ u16 idl; /* 0x04 ID High */
+ u8 data[8]; /* 0x06 8 Byte Data Field */
+ u16 res; /* 0x0E */
+#else
+ u16 ctrl; /* 0x00 Control/Status */
+ u16 tmstamp; /* 0x02 Timestamp */
+ u32 id; /* 0x04 Identifier */
+ u8 data[8]; /* 0x08 8 Byte Data Field */
+#endif
+} can_msg_t;
+
+#ifdef CONFIG_M5282
+/* MSGBUF CTRL */
+#define CAN_MSGBUF_CTRL_CODE(x) (((x) & 0x0F) << 4)
+#define CAN_MSGBUF_CTRL_CODE_MASK (0x0F)
+#define CAN_MSGBUF_CTRL_LEN(x) ((x) & 0x0F)
+#define CAN_MSGBUF_CTRL_LEN_MASK (0xF0)
+
+/* MSGBUF ID */
+#define CAN_MSGBUF_IDH_STD(x) (((x) & 0x07FF) << 5)
+#define CAN_MSGBUF_IDH_STD_MASK (0xE003FFFF)
+#define CAN_MSGBUF_IDH_SRR (0x0010)
+#define CAN_MSGBUF_IDH_IDE (0x0080)
+#define CAN_MSGBUF_IDH_EXTH(x) ((x) & 0x07)
+#define CAN_MSGBUF_IDH_EXTH_MASK (0xFFF8)
+#define CAN_MSGBUF_IDL_EXTL(x) (((x) & 0x7FFF) << 1)
+#define CAN_MSGBUF_IDL_EXTL_MASK (0xFFFE)
+#define CAN_MSGBUF_IDL_RTR (0x0001)
+#else
+/* MSGBUF CTRL */
+#define CAN_MSGBUF_CTRL_CODE(x) (((x) & 0x000F) << 8)
+#define CAN_MSGBUF_CTRL_CODE_MASK (0xF0FF)
+#define CAN_MSGBUF_CTRL_SRR (0x0040)
+#define CAN_MSGBUF_CTRL_IDE (0x0020)
+#define CAN_MSGBUF_CTRL_RTR (0x0010)
+#define CAN_MSGBUF_CTRL_LEN(x) ((x) & 0x000F)
+#define CAN_MSGBUF_CTRL_LEN_MASK (0xFFF0)
+
+/* MSGBUF ID */
+#define CAN_MSGBUF_ID_STD(x) (((x) & 0x000007FF) << 18)
+#define CAN_MSGBUF_ID_STD_MASK (0xE003FFFF)
+#define CAN_MSGBUF_ID_EXT(x) ((x) & 0x0003FFFF)
+#define CAN_MSGBUF_ID_EXT_MASK (0xFFFC0000)
+#endif
+
+/* FlexCan module */
+typedef struct can_ctrl {
+ u32 mcr; /* 0x00 Module Configuration */
+ u32 ctrl; /* 0x04 Control */
+ u32 timer; /* 0x08 Free Running Timer */
+ u32 res1; /* 0x0C */
+ u32 rxgmsk; /* 0x10 Rx Global Mask */
+ u32 rx14msk; /* 0x14 RxBuffer 14 Mask */
+ u32 rx15msk; /* 0x18 RxBuffer 15 Mask */
+#ifdef CONFIG_M5282
+ u32 res2; /* 0x1C */
+ u16 errstat; /* 0x20 Error and status */
+ u16 imsk; /* 0x22 Interrupt Mask */
+ u16 iflag; /* 0x24 Interrupt Flag */
+ u16 errcnt; /* 0x26 Error Counter */
+ u32 res3[3]; /* 0x28 - 0x33 */
+#else
+ u16 res2; /* 0x1C */
+ u16 errcnt; /* 0x1E Error Counter */
+ u16 res3; /* 0x20 */
+ u16 errstat; /* 0x22 Error and status */
+ u32 res4; /* 0x24 */
+ u32 imsk; /* 0x28 Interrupt Mask */
+ u32 res5; /* 0x2C */
+ u16 iflag; /* 0x30 Interrupt Flag */
+#endif
+ u32 res6[19]; /* 0x34 - 0x7F */
+ void *msgbuf; /* 0x80 Message Buffer 0-15 */
+} can_t;
+
+/* MCR */
+#define CAN_MCR_MDIS (0x80000000)
+#define CAN_MCR_FRZ (0x40000000)
+#define CAN_MCR_HALT (0x10000000)
+#define CAN_MCR_NORDY (0x08000000)
+#define CAN_MCF_WAKEMSK (0x04000000) /* 5282 */
+#define CAN_MCR_SOFTRST (0x02000000)
+#define CAN_MCR_FRZACK (0x01000000)
+#define CAN_MCR_SUPV (0x00800000)
+#define CAN_MCR_SELFWAKE (0x00400000) /* 5282 */
+#define CAN_MCR_APS (0x00200000) /* 5282 */
+#define CAN_MCR_LPMACK (0x00100000)
+#define CAN_MCF_BCC (0x00010000)
+#define CAN_MCR_MAXMB(x) ((x) & 0x0F)
+#define CAN_MCR_MAXMB_MASK (0xFFFFFFF0)
+
+/* CTRL */
+#define CAN_CTRL_PRESDIV(x) (((x) & 0xFF) << 24)
+#define CAN_CTRL_PRESDIV_MASK (0x00FFFFFF)
+#define CAN_CTRL_RJW(x) (((x) & 0x03) << 22)
+#define CAN_CTRL_RJW_MASK (0xFF3FFFFF)
+#define CAN_CTRL_PSEG1(x) (((x) & 0x07) << 19)
+#define CAN_CTRL_PSEG1_MASK (0xFFC7FFFF)
+#define CAN_CTRL_PSEG2(x) (((x) & 0x07) << 16)
+#define CAN_CTRL_PSEG2_MASK (0xFFF8FFFF)
+#define CAN_CTRL_BOFFMSK (0x00008000)
+#define CAN_CTRL_ERRMSK (0x00004000)
+#define CAN_CTRL_CLKSRC (0x00002000)
+#define CAN_CTRL_LPB (0x00001000)
+#define CAN_CTRL_RXMODE (0x00000400) /* 5282 */
+#define CAN_CTRL_TXMODE(x) (((x) & 0x03) << 8) /* 5282 */
+#define CAN_CTRL_TXMODE_MASK (0xFFFFFCFF) /* 5282 */
+#define CAN_CTRL_TXMODE_CAN0 (0x00000000) /* 5282 */
+#define CAN_CTRL_TXMODE_CAN1 (0x00000100) /* 5282 */
+#define CAN_CTRL_TXMODE_OPEN (0x00000200) /* 5282 */
+#define CAN_CTRL_SMP (0x00000080)
+#define CAN_CTRL_BOFFREC (0x00000040)
+#define CAN_CTRL_TSYNC (0x00000020)
+#define CAN_CTRL_LBUF (0x00000010)
+#define CAN_CTRL_LOM (0x00000008)
+#define CAN_CTRL_PROPSEG(x) ((x) & 0x07)
+#define CAN_CTRL_PROPSEG_MASK (0xFFFFFFF8)
+
+/* TIMER */
+/* Note: PRESDIV, RJW, PSG1, and PSG2 are part of timer in 5282 */
+#define CAN_TIMER(x) ((x) & 0xFFFF)
+#define CAN_TIMER_MASK (0xFFFF0000)
+
+/* RXGMASK */
+#ifdef CONFIG_M5282
+#define CAN_RXGMSK_MI_STD(x) (((x) & 0x000007FF) << 21)
+#define CAN_RXGMSK_MI_STD_MASK (0x001FFFFF)
+#define CAN_RXGMSK_MI_EXT(x) (((x) & 0x0003FFFF) << 1)
+#define CAN_RXGMSK_MI_EXT_MASK (0xFFF80001)
+#else
+#define CAN_RXGMSK_MI_STD(x) (((x) & 0x000007FF) << 18)
+#define CAN_RXGMSK_MI_STD_MASK (0xE003FFFF)
+#define CAN_RXGMSK_MI_EXT(x) ((x) & 0x0003FFFF)
+#define CAN_RXGMSK_MI_EXT_MASK (0xFFFC0000)
+#endif
+
+/* ERRCNT */
+#define CAN_ERRCNT_RXECTR(x) (((x) & 0xFF) << 8)
+#define CAN_ERRCNT_RXECTR_MASK (0x00FF)
+#define CAN_ERRCNT_TXECTR(x) ((x) & 0xFF)
+#define CAN_ERRCNT_TXECTR_MASK (0xFF00)
+
+/* ERRSTAT */
+#define CAN_ERRSTAT_BITERR1 (0x8000)
+#define CAN_ERRSTAT_BITERR0 (0x4000)
+#define CAN_ERRSTAT_ACKERR (0x2000)
+#define CAN_ERRSTAT_CRCERR (0x1000)
+#define CAN_ERRSTAT_FRMERR (0x0800)
+#define CAN_ERRSTAT_STFERR (0x0400)
+#define CAN_ERRSTAT_TXWRN (0x0200)
+#define CAN_ERRSTAT_RXWRN (0x0100)
+#define CAN_ERRSTAT_IDLE (0x0080)
+#define CAN_ERRSTAT_TXRX (0x0040)
+#define CAN_ERRSTAT_FLT_MASK (0xFFCF)
+#define CAN_ERRSTAT_FLT_BUSOFF (0x0020)
+#define CAN_ERRSTAT_FLT_PASSIVE (0x0010)
+#define CAN_ERRSTAT_FLT_ACTIVE (0x0000)
+#ifdef CONFIG_M5282
+#define CAN_ERRSTAT_BOFFINT (0x0004)
+#define CAN_ERRSTAT_ERRINT (0x0002)
+#else
+#define CAN_ERRSTAT_ERRINT (0x0004)
+#define CAN_ERRSTAT_BOFFINT (0x0002)
+#define CAN_ERRSTAT_WAKEINT (0x0001)
+#endif
+
+/* IMASK */
+#ifdef CONFIG_M5253
+#define CAN_IMASK_BUFnM(x) (1 << (x & 0xFFFFFFFF))
+#define CAN_IMASK_BUFnM_MASKBIT(x) ~CAN_IMASK_BUFnM(x)
+#else
+#define CAN_IMASK_BUFnM(x) (1 << (x & 0xFFFF))
+#define CAN_IMASK_BUFnM_MASKBIT(x) ~CAN_IMASK_BUFnM(x)
+#endif
+
+/* IFLAG */
+#ifdef CONFIG_M5253
+#define CAN_IFLAG_BUFnM(x) (1 << (x & 0xFFFFFFFF))
+#define CAN_IFLAG_BUFnM_MASKBIT(x) ~CAN_IFLAG_BUFnM(x)
+#else
+#define CAN_IFLAG_BUFnM(x) (1 << (x & 0xFFFF))
+#define CAN_IFLAG_BUFnM_MASKBIT(x) ~CAN_IFLAG_BUFnM(x)
+#endif
+
+#endif /* __FLEXCAN_H__ */
diff --git a/include/asm-m68k/coldfire/pwm.h b/include/asm-m68k/coldfire/pwm.h
new file mode 100644
index 0000000..f737d98
--- /dev/null
+++ b/include/asm-m68k/coldfire/pwm.h
@@ -0,0 +1,115 @@
+/*
+ * Pulse Width Modulation Memory Map
+ *
+ * Copyright (C) 2004-2008 Freescale Semiconductor, Inc.
+ * TsiChung Liew ([EMAIL PROTECTED])
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __ATA_H__
+#define __ATA_H__
+
+/* Pulse Width Modulation (PWM) */
+typedef struct pwm_ctrl {
+#ifdef CONFIG_M5272
+ u8 cr0;
+ u8 res1[3];
+ u8 cr1;
+ u8 res2[3];
+ u8 cr2;
+ u8 res3[7];
+ u8 pwr0;
+ u8 res4[3];
+ u8 pwr1;
+ u8 res5[3];
+ u8 pwr2;
+ u8 res6[7];
+#else
+ u8 en; /* 0x00 PWM Enable */
+ u8 pol; /* 0x01 Polarity */
+ u8 clk; /* 0x02 Clock Select */
+ u8 prclk; /* 0x03 Prescale Clock Select */
+ u8 cae; /* 0x04 Center Align Enable */
+ u8 ctl; /* 0x05 Control */
+ u16 res1; /* 0x06 - 0x07 */
+ u8 scla; /* 0x08 Scale A */
+ u8 sclb; /* 0x09 Scale B */
+ u16 res2; /* 0x0A - 0x0B */
+#ifdef CONFIG_M5275
+ u8 cnt[4]; /* 0x0C Channel n Counter */
+ u16 res3; /* 0x10 - 0x11 */
+ u8 per[4]; /* 0x14 Channel n Period */
+ u16 res4; /* 0x16 - 0x17 */
+ u8 dty[4]; /* 0x18 Channel n Duty */
+#else
+ u8 cnt[8]; /* 0x0C Channel n Counter */
+ u8 per[8]; /* 0x14 Channel n Period */
+ u8 dty[8]; /* 0x1C Channel n Duty */
+ u8 sdn; /* 0x24 Shutdown */
+ u8 res3[3]; /* 0x25 - 0x27 */
+#endif /* CONFIG_M5275 */
+#endif /* CONFIG_M5272 */
+} pwm_t;
+
+#ifdef CONFIG_M5272
+
+#define PWM_CR_EN (0x80)
+#define PWM_CR_FRC1 (0x40)
+#define PWM_CR_LVL (0x20)
+#define PWM_CR_CLKSEL(x) ((x) & 0x0F)
+#define PWM_CR_CLKSEL_MASK (0xF0)
+
+#else
+
+#define PWM_EN_PWMEn(x) (1 << ((x) & 0x07))
+#define PWM_EN_PWMEn_MASK (0xF0)
+
+#define PWM_POL_PPOLn(x) (1 << ((x) & 0x07))
+#define PWM_POL_PPOLn_MASK (0xF0)
+
+#define PWM_CLK_PCLKn(x) (1 << ((x) & 0x07))
+#define PWM_CLK_PCLKn_MASK (0xF0)
+
+#define PWM_PRCLK_PCKB(x) (((x) & 0x07) << 4)
+#define PWM_PRCLK_PCKB_MASK (0x8F)
+#define PWM_PRCLK_PCKA(x) ((x) & 0x07)
+#define PWM_PRCLK_PCKA_MASK (0xF8)
+
+#define PWM_CLK_PCLKn(x) (1 << ((x) & 0x07))
+#define PWM_CLK_PCLKn_MASK (0xF0)
+
+#define PWM_CTL_CON67 (0x80)
+#define PWM_CTL_CON45 (0x40)
+#define PWM_CTL_CON23 (0x20)
+#define PWM_CTL_CON01 (0x10)
+#define PWM_CTL_PSWAR (0x08)
+#define PWM_CTL_PFRZ (0x04)
+
+#define PWM_SDN_IF (0x80)
+#define PWM_SDN_IE (0x40)
+#define PWM_SDN_RESTART (0x20)
+#define PWM_SDN_LVL (0x10)
+#define PWM_SDN_PWM7IN (0x04)
+#define PWM_SDN_PWM7IL (0x02)
+#define PWM_SDN_SDNEN (0x01)
+
+#endif /* CONFIG_M5272 */
+
+#endif /* __ATA_H__ */
diff --git a/include/asm-m68k/immap_5227x.h b/include/asm-m68k/immap_5227x.h
index df1ec4a..45f62a4 100644
--- a/include/asm-m68k/immap_5227x.h
+++ b/include/asm-m68k/immap_5227x.h
@@ -71,7 +71,9 @@
#include <asm/coldfire/edma.h>
#include <asm/coldfire/eport.h>
#include <asm/coldfire/flexbus.h>
+#include <asm/coldfire/flexcan.h>
#include <asm/coldfire/lcd.h>
+#include <asm/coldfire/pwm.h>
#include <asm/coldfire/ssi.h>
/* Interrupt Controller (INTC) */
@@ -184,6 +186,12 @@ typedef struct ccm {
u16 sbfcr; /* Serial Boot Control */
} ccm_t;
+typedef struct canex_ctrl {
+ can_msg_t msg[16]; /* 0x00 Message Buffer 0-15 */
+ u32 res0[0x700]; /* 0x100 */
+ can_msg_t rxim[16]; /* 0x800 Rx Individual Mask 0-15 */
+} canex_t;
+
/* General Purpose I/O Module (GPIO) */
typedef struct gpio {
/* Port Output Data Registers */
diff --git a/include/asm-m68k/immap_5235.h b/include/asm-m68k/immap_5235.h
index dfab416..8fdf32a 100644
--- a/include/asm-m68k/immap_5235.h
+++ b/include/asm-m68k/immap_5235.h
@@ -64,6 +64,7 @@
#define MMAP_CAN2 (CONFIG_SYS_MBAR + 0x001F0000)
#include <asm/coldfire/eport.h>
+#include <asm/coldfire/flexcan.h>
#include <asm/coldfire/qspi.h>
/* System Control Module register */
@@ -227,6 +228,10 @@ typedef struct intgack_ctrl1 {
u8 Lniack[7]; /* 0xE1 - 0xE7 Global Level 0 Interrupt
Acknowledge */
} intgack_t;
+typedef struct canex_ctrl {
+ can_msg_t msg[16]; /* 0x00 Message Buffer 0-15 */
+} canex_t;
+
/* GPIO port registers */
typedef struct gpio_ctrl {
/* Port Output Data Registers */
@@ -343,23 +348,4 @@ typedef struct wdog_ctrl {
u16 sr; /* 0x06 Service register */
} wdog_t;
-/* FlexCan module registers */
-typedef struct can_ctrl {
- u32 mcr; /* 0x00 Module Configuration register */
- u32 ctrl; /* 0x04 Control register */
- u32 timer; /* 0x08 Free Running Timer */
- u32 res1; /* 0x0C */
- u32 rxgmask; /* 0x10 Rx Global Mask */
- u32 rx14mask; /* 0x14 RxBuffer 14 Mask */
- u32 rx15mask; /* 0x18 RxBuffer 15 Mask */
- u32 errcnt; /* 0x1C Error Counter Register */
- u32 errstat; /* 0x20 Error and status Register */
- u32 res2; /* 0x24 */
- u32 imask; /* 0x28 Interrupt Mask Register */
- u32 res3; /* 0x2C */
- u32 iflag; /* 0x30 Interrupt Flag Register */
- u32 res4[19]; /* 0x34 - 0x7F */
- u32 MB0_15[2048]; /* 0x80 Message Buffer 0-15 */
-} can_t;
-
#endif /* __IMMAP_5235__ */
diff --git a/include/asm-m68k/immap_5253.h b/include/asm-m68k/immap_5253.h
index fa09923..bf30189 100644
--- a/include/asm-m68k/immap_5253.h
+++ b/include/asm-m68k/immap_5253.h
@@ -23,8 +23,8 @@
* MA 02111-1307 USA
*/
-#ifndef __IMMAP_5249__
-#define __IMMAP_5249__
+#ifndef __IMMAP_5253__
+#define __IMMAP_5253__
#define MMAP_INTC (CONFIG_SYS_MBAR + 0x00000040)
#define MMAP_DTMR0 (CONFIG_SYS_MBAR + 0x00000140)
@@ -40,6 +40,11 @@
#define MMAP_UART2 (CONFIG_SYS_MBAR2 + 0x00000C00)
#include <asm/coldfire/ata.h>
+#include <asm/coldfire/flexcan.h>
#include <asm/coldfire/qspi.h>
-#endif /* __IMMAP_5249__ */
+typedef struct canex_ctrl {
+ can_msg_t msg[32]; /* 0x80 Message Buffer 0-31 */
+} canex_t;
+
+#endif /* __IMMAP_5253__ */
diff --git a/include/asm-m68k/immap_5272.h b/include/asm-m68k/immap_5272.h
index d904053..8d4254b 100644
--- a/include/asm-m68k/immap_5272.h
+++ b/include/asm-m68k/immap_5272.h
@@ -44,6 +44,8 @@
#define MMAP_FEC (CONFIG_SYS_MBAR + 0x00000840)
#define MMAP_USB (CONFIG_SYS_MBAR + 0x00001000)
+#include <asm/coldfire/pwm.h>
+
/* System configuration registers */
typedef struct sys_ctrl {
uint sc_mbar;
@@ -104,22 +106,6 @@ typedef struct gpio_ctrl {
uchar res2[4];
} gpio_t;
-/* PWM module registers */
-typedef struct pwm_ctrl {
- uchar pwm_pwcr0;
- uchar res1[3];
- uchar pwm_pwcr1;
- uchar res2[3];
- uchar pwm_pwcr2;
- uchar res3[7];
- uchar pwm_pwwd0;
- uchar res4[3];
- uchar pwm_pwwd1;
- uchar res5[3];
- uchar pwm_pwwd2;
- uchar res6[7];
-} pwm_t;
-
/* DMA module registers */
typedef struct dma_ctrl {
ulong dma_dmr;
diff --git a/include/asm-m68k/immap_5275.h b/include/asm-m68k/immap_5275.h
index 72846fc..90143c8 100644
--- a/include/asm-m68k/immap_5275.h
+++ b/include/asm-m68k/immap_5275.h
@@ -67,6 +67,7 @@
#define MMAP_PWM0 (CONFIG_SYS_MBAR + 0x001D0000)
#include <asm/coldfire/eport.h>
+#include <asm/coldfire/pwm.h>
#include <asm/coldfire/qspi.h>
/* System configuration registers
@@ -311,23 +312,6 @@ typedef struct gpio_ctrl {
} gpio_t;
-/* PWM module registers
- */
-typedef struct pwm_ctrl {
- u8 pwcr0;
- u8 res1[3];
- u8 pwcr1;
- u8 res2[3];
- u8 pwcr2;
- u8 res3[7];
- u8 pwwd0;
- u8 res4[3];
- u8 pwwd1;
- u8 res5[3];
- u8 pwwd2;
- u8 res6[7];
-} pwm_t;
-
/* Watchdog registers
*/
typedef struct wdog_ctrl {
diff --git a/include/asm-m68k/immap_5282.h b/include/asm-m68k/immap_5282.h
index 417502d..8f27556 100644
--- a/include/asm-m68k/immap_5282.h
+++ b/include/asm-m68k/immap_5282.h
@@ -63,6 +63,7 @@
#define MMAP_CFMMEM (CONFIG_SYS_MBAR + 0x04000000)
#include <asm/coldfire/eport.h>
+#include <asm/coldfire/flexcan.h>
#include <asm/coldfire/qspi.h>
/* System Control Module */
@@ -95,6 +96,10 @@ typedef struct scm_ctrl {
u16 res8;
} scm_t;
+typedef struct canex_ctrl {
+ can_msg_t msg[16]; /* 0x00 Message Buffer 0-15 */
+} canex_t;
+
/* Flexbus module Chip select registers */
typedef struct fbcs_ctrl {
u16 csar0; /* 0x00 Chip-Select Address Register 0 */
diff --git a/include/asm-m68k/immap_5329.h b/include/asm-m68k/immap_5329.h
index 88f9b20..c32caf5 100644
--- a/include/asm-m68k/immap_5329.h
+++ b/include/asm-m68k/immap_5329.h
@@ -73,7 +73,9 @@
#include <asm/coldfire/eport.h>
#include <asm/coldfire/qspi.h>
#include <asm/coldfire/flexbus.h>
+#include <asm/coldfire/flexcan.h>
#include <asm/coldfire/lcd.h>
+#include <asm/coldfire/pwm.h>
#include <asm/coldfire/ssi.h>
/* System control module registers */
@@ -167,24 +169,6 @@ typedef struct scm2_ctrl {
u32 bmt1; /* 0x54 Bus Monitor Timeout 1 */
} scm2_t;
-/* FlexCan module registers */
-typedef struct can_ctrl {
- u32 mcr; /* 0x00 Module Configuration register */
- u32 ctrl; /* 0x04 Control register */
- u32 timer; /* 0x08 Free Running Timer */
- u32 res1; /* 0x0C */
- u32 rxgmask; /* 0x10 Rx Global Mask */
- u32 rx14mask; /* 0x14 RxBuffer 14 Mask */
- u32 rx15mask; /* 0x18 RxBuffer 15 Mask */
- u32 errcnt; /* 0x1C Error Counter Register */
- u32 errstat; /* 0x20 Error and status Register */
- u32 res2; /* 0x24 */
- u32 imask; /* 0x28 Interrupt Mask Register */
- u32 res3; /* 0x2C */
- u32 iflag; /* 0x30 Interrupt Flag Register */
- u32 res4[19]; /* 0x34 - 0x7F */
- u32 MB0_15[2048]; /* 0x80 Message Buffer 0-15 */
-} can_t;
/* System Control Module register 3 */
typedef struct scm3_ctrl {
@@ -208,6 +192,10 @@ typedef struct scm3_ctrl {
u32 cfdtr; /* 0x7C Core Fault Data Register */
} scm3_t;
+typedef struct canex_ctrl {
+ can_msg_t msg[16]; /* 0x00 Message Buffer 0-15 */
+} canex_t;
+
/* Interrupt module registers */
typedef struct int0_ctrl {
/* Interrupt Controller 0 */
@@ -284,46 +272,6 @@ typedef struct intgack_ctrl1 {
u8 Lniack[7]; /* 0xE1 - 0xE7 Global Level 0 Interrupt
Acknowledge */
} intgack_t;
-/* PWM module registers */
-typedef struct pwm_ctrl {
- u8 en; /* 0x00 PWM Enable Register */
- u8 pol; /* 0x01 Polarity Register */
- u8 clk; /* 0x02 Clock Select Register */
- u8 prclk; /* 0x03 Prescale Clock Select Register */
- u8 cae; /* 0x04 Center Align Enable Register */
- u8 ctl; /* 0x05 Control Register */
- u8 res1[2]; /* 0x06 - 0x07 */
- u8 scla; /* 0x08 Scale A register */
- u8 sclb; /* 0x09 Scale B register */
- u8 res2[2]; /* 0x0A - 0x0B */
- u8 cnt0; /* 0x0C Channel 0 Counter register */
- u8 cnt1; /* 0x0D Channel 1 Counter register */
- u8 cnt2; /* 0x0E Channel 2 Counter register */
- u8 cnt3; /* 0x0F Channel 3 Counter register */
- u8 cnt4; /* 0x10 Channel 4 Counter register */
- u8 cnt5; /* 0x11 Channel 5 Counter register */
- u8 cnt6; /* 0x12 Channel 6 Counter register */
- u8 cnt7; /* 0x13 Channel 7 Counter register */
- u8 per0; /* 0x14 Channel 0 Period register */
- u8 per1; /* 0x15 Channel 1 Period register */
- u8 per2; /* 0x16 Channel 2 Period register */
- u8 per3; /* 0x17 Channel 3 Period register */
- u8 per4; /* 0x18 Channel 4 Period register */
- u8 per5; /* 0x19 Channel 5 Period register */
- u8 per6; /* 0x1A Channel 6 Period register */
- u8 per7; /* 0x1B Channel 7 Period register */
- u8 dty0; /* 0x1C Channel 0 Duty register */
- u8 dty1; /* 0x1D Channel 1 Duty register */
- u8 dty2; /* 0x1E Channel 2 Duty register */
- u8 dty3; /* 0x1F Channel 3 Duty register */
- u8 dty4; /* 0x20 Channel 4 Duty register */
- u8 dty5; /* 0x21 Channel 5 Duty register */
- u8 dty6; /* 0x22 Channel 6 Duty register */
- u8 dty7; /* 0x23 Channel 7 Duty register */
- u8 sdn; /* 0x24 Shutdown register */
- u8 res3[3]; /* 0x25 - 0x27 */
-} pwm_t;
-
/* Watchdog registers */
typedef struct wdog_ctrl {
u16 cr; /* 0x00 Control register */
diff --git a/include/asm-m68k/immap_547x_8x.h b/include/asm-m68k/immap_547x_8x.h
index f11b61a..1dccc77 100644
--- a/include/asm-m68k/immap_547x_8x.h
+++ b/include/asm-m68k/immap_547x_8x.h
@@ -60,6 +60,7 @@
#include <asm/coldfire/dspi.h>
#include <asm/coldfire/eport.h>
#include <asm/coldfire/flexbus.h>
+#include <asm/coldfire/flexcan.h>
typedef struct siu {
u32 mbar; /* 0x00 */
@@ -149,6 +150,11 @@ typedef struct gptmr {
u8 intr; /* Interrupts */
} gptmr_t;
+typedef struct canex_ctrl {
+ can_msg_t msg[16]; /* 0x00 Message Buffer 0-15 */
+} canex_t;
+
+
typedef struct slt {
u32 tcnt; /* 0x00 */
u32 cr; /* 0x04 */
diff --git a/include/asm-m68k/m5235.h b/include/asm-m68k/m5235.h
index e4880c0..f549fb9 100644
--- a/include/asm-m68k/m5235.h
+++ b/include/asm-m68k/m5235.h
@@ -718,97 +718,4 @@
#define WTM_WCR_HALTED (0x0002)
#define WTM_WCR_EN (0x0001)
-/*********************************************************************
-* FlexCAN Module (CAN)
-*********************************************************************/
-/* Bit definitions and macros for CAN_CANMCR */
-#define CANMCR_MDIS (0x80000000)
-#define CANMCR_FRZ (0x40000000)
-#define CANMCR_HALT (0x10000000)
-#define CANMCR_NORDY (0x08000000)
-#define CANMCR_SOFTRST (0x02000000)
-#define CANMCR_FRZACK (0x01000000)
-#define CANMCR_SUPV (0x00800000)
-#define CANMCR_LPMACK (0x00100000)
-#define CANMCR_MAXMB(x) (((x)&0x0F))
-
-/* Bit definitions and macros for CAN_CANCTRL */
-#define CANCTRL_PRESDIV(x) (((x)&0xFF)<<24)
-#define CANCTRL_RJW(x) (((x)&0x03)<<22)
-#define CANCTRL_PSEG1(x) (((x)&0x07)<<19)
-#define CANCTRL_PSEG2(x) (((x)&0x07)<<16)
-#define CANCTRL_BOFFMSK (0x00008000)
-#define CANCTRL_ERRMSK (0x00004000)
-#define CANCTRL_CLKSRC (0x00002000)
-#define CANCTRL_LPB (0x00001000)
-#define CANCTRL_SMP (0x00000080)
-#define CANCTRL_BOFFREC (0x00000040)
-#define CANCTRL_TSYNC (0x00000020)
-#define CANCTRL_LBUF (0x00000010)
-#define CANCTRL_LOM (0x00000008)
-#define CANCTRL_PROPSEG(x) (((x)&0x07))
-
-/* Bit definitions and macros for CAN_TIMER */
-#define TIMER_TIMER(x) ((x)&0xFFFF)
-
-/* Bit definitions and macros for CAN_RXGMASK */
-#define RXGMASK_MI(x) ((x)&0x1FFFFFFF)
-
-/* Bit definitions and macros for CAN_ERRCNT */
-#define ERRCNT_TXECTR(x) (((x)&0xFF))
-#define ERRCNT_RXECTR(x) (((x)&0xFF)<<8)
-
-/* Bit definitions and macros for CAN_ERRSTAT */
-#define ERRSTAT_BITERR1 (0x00008000)
-#define ERRSTAT_BITERR0 (0x00004000)
-#define ERRSTAT_ACKERR (0x00002000)
-#define ERRSTAT_CRCERR (0x00001000)
-#define ERRSTAT_FRMERR (0x00000800)
-#define ERRSTAT_STFERR (0x00000400)
-#define ERRSTAT_TXWRN (0x00000200)
-#define ERRSTAT_RXWRN (0x00000100)
-#define ERRSTAT_IDLE (0x00000080)
-#define ERRSTAT_TXRX (0x00000040)
-#define ERRSTAT_FLT_BUSOFF (0x00000020)
-#define ERRSTAT_FLT_PASSIVE (0x00000010)
-#define ERRSTAT_FLT_ACTIVE (0x00000000)
-#define ERRSTAT_BOFFINT (0x00000004)
-#define ERRSTAT_ERRINT (0x00000002)
-
-/* Bit definitions and macros for CAN_IMASK */
-#define IMASK_BUF15M (0x00008000)
-#define IMASK_BUF14M (0x00004000)
-#define IMASK_BUF13M (0x00002000)
-#define IMASK_BUF12M (0x00001000)
-#define IMASK_BUF11M (0x00000800)
-#define IMASK_BUF10M (0x00000400)
-#define IMASK_BUF9M (0x00000200)
-#define IMASK_BUF8M (0x00000100)
-#define IMASK_BUF7M (0x00000080)
-#define IMASK_BUF6M (0x00000040)
-#define IMASK_BUF5M (0x00000020)
-#define IMASK_BUF4M (0x00000010)
-#define IMASK_BUF3M (0x00000008)
-#define IMASK_BUF2M (0x00000004)
-#define IMASK_BUF1M (0x00000002)
-#define IMASK_BUF0M (0x00000001)
-
-/* Bit definitions and macros for CAN_IFLAG */
-#define IFLAG_BUF15I (0x00008000)
-#define IFLAG_BUF14I (0x00004000)
-#define IFLAG_BUF13I (0x00002000)
-#define IFLAG_BUF12I (0x00001000)
-#define IFLAG_BUF11I (0x00000800)
-#define IFLAG_BUF10I (0x00000400)
-#define IFLAG_BUF9I (0x00000200)
-#define IFLAG_BUF8I (0x00000100)
-#define IFLAG_BUF7I (0x00000080)
-#define IFLAG_BUF6I (0x00000040)
-#define IFLAG_BUF5I (0x00000020)
-#define IFLAG_BUF4I (0x00000010)
-#define IFLAG_BUF3I (0x00000008)
-#define IFLAG_BUF2I (0x00000004)
-#define IFLAG_BUF1I (0x00000002)
-#define IFLAG_BUF0I (0x00000001)
-
#endif /* mcf5235_h */
diff --git a/include/asm-m68k/m5329.h b/include/asm-m68k/m5329.h
index b05da52..16a50b2 100644
--- a/include/asm-m68k/m5329.h
+++ b/include/asm-m68k/m5329.h
@@ -261,100 +261,6 @@
#define RCM_RSR_SOFT (0x20)
/*********************************************************************
-* FlexCAN Module (CAN)
-*********************************************************************/
-/* Bit definitions and macros for CAN_CANMCR */
-#define CANMCR_MDIS (0x80000000)
-#define CANMCR_FRZ (0x40000000)
-#define CANMCR_HALT (0x10000000)
-#define CANMCR_NORDY (0x08000000)
-#define CANMCR_SOFTRST (0x02000000)
-#define CANMCR_FRZACK (0x01000000)
-#define CANMCR_SUPV (0x00800000)
-#define CANMCR_LPMACK (0x00100000)
-#define CANMCR_MAXMB(x) (((x)&0x0F))
-
-/* Bit definitions and macros for CAN_CANCTRL */
-#define CANCTRL_PRESDIV(x) (((x)&0xFF)<<24)
-#define CANCTRL_RJW(x) (((x)&0x03)<<22)
-#define CANCTRL_PSEG1(x) (((x)&0x07)<<19)
-#define CANCTRL_PSEG2(x) (((x)&0x07)<<16)
-#define CANCTRL_BOFFMSK (0x00008000)
-#define CANCTRL_ERRMSK (0x00004000)
-#define CANCTRL_CLKSRC (0x00002000)
-#define CANCTRL_LPB (0x00001000)
-#define CANCTRL_SMP (0x00000080)
-#define CANCTRL_BOFFREC (0x00000040)
-#define CANCTRL_TSYNC (0x00000020)
-#define CANCTRL_LBUF (0x00000010)
-#define CANCTRL_LOM (0x00000008)
-#define CANCTRL_PROPSEG(x) (((x)&0x07))
-
-/* Bit definitions and macros for CAN_TIMER */
-#define TIMER_TIMER(x) ((x)&0xFFFF)
-
-/* Bit definitions and macros for CAN_RXGMASK */
-#define RXGMASK_MI(x) ((x)&0x1FFFFFFF)
-
-/* Bit definitions and macros for CAN_ERRCNT */
-#define ERRCNT_TXECTR(x) (((x)&0xFF))
-#define ERRCNT_RXECTR(x) (((x)&0xFF)<<8)
-
-/* Bit definitions and macros for CAN_ERRSTAT */
-#define ERRSTAT_BITERR1 (0x00008000)
-#define ERRSTAT_BITERR0 (0x00004000)
-#define ERRSTAT_ACKERR (0x00002000)
-#define ERRSTAT_CRCERR (0x00001000)
-#define ERRSTAT_FRMERR (0x00000800)
-#define ERRSTAT_STFERR (0x00000400)
-#define ERRSTAT_TXWRN (0x00000200)
-#define ERRSTAT_RXWRN (0x00000100)
-#define ERRSTAT_IDLE (0x00000080)
-#define ERRSTAT_TXRX (0x00000040)
-#define ERRSTAT_FLT_BUSOFF (0x00000020)
-#define ERRSTAT_FLT_PASSIVE (0x00000010)
-#define ERRSTAT_FLT_ACTIVE (0x00000000)
-#define ERRSTAT_BOFFINT (0x00000004)
-#define ERRSTAT_ERRINT (0x00000002)
-#define ERRSTAT_WAKINT (0x00000001)
-
-/* Bit definitions and macros for CAN_IMASK */
-#define IMASK_BUF15M (0x00008000)
-#define IMASK_BUF14M (0x00004000)
-#define IMASK_BUF13M (0x00002000)
-#define IMASK_BUF12M (0x00001000)
-#define IMASK_BUF11M (0x00000800)
-#define IMASK_BUF10M (0x00000400)
-#define IMASK_BUF9M (0x00000200)
-#define IMASK_BUF8M (0x00000100)
-#define IMASK_BUF7M (0x00000080)
-#define IMASK_BUF6M (0x00000040)
-#define IMASK_BUF5M (0x00000020)
-#define IMASK_BUF4M (0x00000010)
-#define IMASK_BUF3M (0x00000008)
-#define IMASK_BUF2M (0x00000004)
-#define IMASK_BUF1M (0x00000002)
-#define IMASK_BUF0M (0x00000001)
-
-/* Bit definitions and macros for CAN_IFLAG */
-#define IFLAG_BUF15I (0x00008000)
-#define IFLAG_BUF14I (0x00004000)
-#define IFLAG_BUF13I (0x00002000)
-#define IFLAG_BUF12I (0x00001000)
-#define IFLAG_BUF11I (0x00000800)
-#define IFLAG_BUF10I (0x00000400)
-#define IFLAG_BUF9I (0x00000200)
-#define IFLAG_BUF8I (0x00000100)
-#define IFLAG_BUF7I (0x00000080)
-#define IFLAG_BUF6I (0x00000040)
-#define IFLAG_BUF5I (0x00000020)
-#define IFLAG_BUF4I (0x00000010)
-#define IFLAG_BUF3I (0x00000008)
-#define IFLAG_BUF2I (0x00000004)
-#define IFLAG_BUF1I (0x00000002)
-#define IFLAG_BUF0I (0x00000001)
-
-/*********************************************************************
* Interrupt Controller (INTC)
*********************************************************************/
#define INTC0_EPORT INTC_IPRL_INT1
@@ -507,54 +413,6 @@
#define INTC_ICR_IL(x) ((x)&0x07)
/*********************************************************************
-* Pulse Width Modulation (PWM)
-*********************************************************************/
-/* Bit definitions and macros for PWM_E */
-#define PWM_EN_PWME7 (0x80)
-#define PWM_EN_PWME5 (0x20)
-#define PWM_EN_PWME3 (0x08)
-#define PWM_EN_PWME1 (0x02)
-
-/* Bit definitions and macros for PWM_POL */
-#define PWM_POL_PPOL7 (0x80)
-#define PWM_POL_PPOL5 (0x20)
-#define PWM_POL_PPOL3 (0x08)
-#define PWM_POL_PPOL1 (0x02)
-
-/* Bit definitions and macros for PWM_CLK */
-#define PWM_CLK_PCLK7 (0x80)
-#define PWM_CLK_PCLK5 (0x20)
-#define PWM_CLK_PCLK3 (0x08)
-#define PWM_CLK_PCLK1 (0x02)
-
-/* Bit definitions and macros for PWM_PRCLK */
-#define PWM_PRCLK_PCKB(x) (((x)&0x07)<<4)
-#define PWM_PRCLK_PCKA(x) ((x)&0x07)
-
-/* Bit definitions and macros for PWM_CAE */
-#define PWM_CAE_CAE7 (0x80)
-#define PWM_CAE_CAE5 (0x20)
-#define PWM_CAE_CAE3 (0x08)
-#define PWM_CAE_CAE1 (0x02)
-
-/* Bit definitions and macros for PWM_CTL */
-#define PWM_CTL_CON67 (0x80)
-#define PWM_CTL_CON45 (0x40)
-#define PWM_CTL_CON23 (0x20)
-#define PWM_CTL_CON01 (0x10)
-#define PWM_CTL_PSWAR (0x08)
-#define PWM_CTL_PFRZ (0x04)
-
-/* Bit definitions and macros for PWM_SDN */
-#define PWM_SDN_IF (0x80)
-#define PWM_SDN_IE (0x40)
-#define PWM_SDN_RESTART (0x20)
-#define PWM_SDN_LVL (0x10)
-#define PWM_SDN_PWM7IN (0x04)
-#define PWM_SDN_PWM7IL (0x02)
-#define PWM_SDN_SDNEN (0x01)
-
-/*********************************************************************
* Watchdog Timer Modules (WTM)
*********************************************************************/
/* Bit definitions and macros for WTM_WCR */
--
1.5.6.4
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