Rather than hardcoding MDCDIV to 24 (which is correct for ~125mhz SCLK),
use the real algorithm so it gets set correctly regardless of SCLK.
Signed-off-by: Mike Frysinger <vap...@gentoo.org>
CC: Ben Warren <biggerbadder...@gmail.com>
---
drivers/net/bfin_mac.c | 10 +++++-----
1 files changed, 5 insertions(+), 5 deletions(-)
diff --git a/drivers/net/bfin_mac.c b/drivers/net/bfin_mac.c
index f074f17..427478f 100644
--- a/drivers/net/bfin_mac.c
+++ b/drivers/net/bfin_mac.c
@@ -345,9 +345,12 @@ static void SoftResetPHY(void)
}
#endif
+/* MDC = SCLK / MDC_freq / 2 - 1 */
+#define MDC_FREQ_TO_DIV(mdc_freq) (get_sclk() / (mdc_freq) / 2 - 1)
+
static int SetupSystemRegs(int *opmode)
{
- u16 sysctl, phydat;
+ u16 phydat;
int count = 0;
/* Enable PHY output */
*pVR_CTL |= CLKBUFOE;
@@ -390,12 +393,9 @@ static int SetupSystemRegs(int *opmode)
# endif
#endif
- /* MDC = 2.5 MHz */
- sysctl = SET_MDCDIV(24);
/* Odd word alignment for Receive Frame DMA word */
/* Configure checksum support and rcve frame word alignment */
- sysctl |= RXDWA | RXCKS;
- *pEMAC_SYSCTL = sysctl;
+ *pEMAC_SYSCTL = RXDWA | RXCKS | SET_MDCDIV(MDC_FREQ_TO_DIV(2500000));
/* auto negotiation on */
/* full duplex */
/* 100 Mbps */
--
1.6.1.1
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