Rev 3 and earlier stay with Micron memory settings. Rev 4 and later
will default to Elpida settings. CONFIG_ELPIDA forces these setting
and will run slightly more slowly. CONFIG_MICRON will force Micron
settings. If Micron settings are used, if a memory test fails, it
will revert to the slower Elpida settings
Signed-off-by: Martha Marx <mm...@silicontkx.com>
---
board/ads5121/ads5121.c | 154 ++++++++++++++++++++++++++++++++++++---------
include/configs/ads5121.h | 41 +++++++-----
2 files changed, 150 insertions(+), 45 deletions(-)
diff --git a/board/ads5121/ads5121.c b/board/ads5121/ads5121.c
index 6c40e94..deb4a74 100644
--- a/board/ads5121/ads5121.c
+++ b/board/ads5121/ads5121.c
@@ -120,13 +120,53 @@ phys_size_t initdram (int board_type)
return msize;
}
+int simple_mem_check()
+{
+ volatile u32 val;
+ volatile u32 *addr;
+ int i, j;
+ u32 save[32];
+
+ /*
+ * Very very simple non-destructive check for operational RAM.
+ */
+ j = 0;
+ for (i = CONFIG_SYS_DDR_SIZE / sizeof (long); i > 0; i >>= 1) {
+ addr = (volatile u32 *) CONFIG_SYS_DDR_BASE + i;
+ save[j++] = *addr;
+ *addr = ~i;
+ }
+
+ addr = (volatile u32 *) CONFIG_SYS_DDR_BASE;
+ save[j] = *addr;
+ *addr = 0xdeadbeef;
+ val = *addr;
+ *addr = save[j];
+
+ if (val != 0xdeadbeef)
+ return (0);
+
+ for (i = 1; i <= CONFIG_SYS_DDR_SIZE / sizeof (long); i <<= 1) {
+ addr = (volatile u32 *) CONFIG_SYS_DDR_BASE + i;
+ val = *addr;
+ *addr = save[--j];
+ if (val != ~i)
+ return (0);
+ }
+ return(1);
+}
+
/*
* fixed sdram init -- the board doesn't use memory modules that have serial
presence
* detect or similar mechanism for discovery of the DRAM settings
*/
+
long int fixed_sdram (void)
{
+ u32 try_elpida;
volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
+ ushort brd_rev = *(vu_short *) (CONFIG_SYS_CPLD_BASE + 0x00);
+
u32 msize = CONFIG_SYS_DDR_SIZE * 1024 * 1024;
u32 msize_log2 = __ilog2 (msize);
u32 i;
@@ -174,41 +214,97 @@ long int fixed_sdram (void)
im->mddrc.lut_table4_alternate_upper = CONFIG_SYS_MDDRCGRP_LUT4_AU;
im->mddrc.lut_table4_alternate_lower = CONFIG_SYS_MDDRCGRP_LUT4_AL;
+#ifdef CONFIG_MICRON
+/* forces Micron settings - on rev 4 boards will retry w/Elpida if necessary */
+ try_elpida = 0;
+#elif defined(CONFIG_ELPIDA)
+/* forces Elpida settings w/slower CAS - works w/ both Micron and Elpida rev4
*/
+ try_elpida = 1;
+#else
+ if (brd_rev >= 0x0400)
+ try_elpida = 1;
+ else
+ try_elpida = 0;
+#endif
+retry:
+ debug("Use %s Memory settings\n\t", try_elpida ? "Elpida" : "Micron");
+
/* Initialize MDDRC */
- im->mddrc.ddr_sys_config = CONFIG_SYS_MDDRC_SYS_CFG;
- im->mddrc.ddr_time_config0 = CONFIG_SYS_MDDRC_TIME_CFG0;
- im->mddrc.ddr_time_config1 = CONFIG_SYS_MDDRC_TIME_CFG1;
- im->mddrc.ddr_time_config2 = CONFIG_SYS_MDDRC_TIME_CFG2;
+ if (try_elpida) {
+ im->mddrc.ddr_sys_config = CONFIG_SYS_MDDRC_SYS_CFG_ELPIDA;
+ im->mddrc.ddr_time_config0 = CONFIG_SYS_MDDRC_TIME_CFG0;
+ im->mddrc.ddr_time_config1 = CONFIG_SYS_MDDRC_TIME_CFG1_ELPIDA;
+ im->mddrc.ddr_time_config2 = CONFIG_SYS_MDDRC_TIME_CFG2_ELPIDA;
+ } else {
+ im->mddrc.ddr_sys_config = CONFIG_SYS_MDDRC_SYS_CFG_MICRON;
+ im->mddrc.ddr_time_config0 = CONFIG_SYS_MDDRC_TIME_CFG0;
+ im->mddrc.ddr_time_config1 = CONFIG_SYS_MDDRC_TIME_CFG1_MICRON;
+ im->mddrc.ddr_time_config2 = CONFIG_SYS_MDDRC_TIME_CFG2_MICRON;
+ }
/* Initialize DDR */
for (i = 0; i < 10; i++)
- im->mddrc.ddr_command = CONFIG_SYS_MICRON_NOP;
-
- im->mddrc.ddr_command = CONFIG_SYS_MICRON_PCHG_ALL;
- im->mddrc.ddr_command = CONFIG_SYS_MICRON_NOP;
- im->mddrc.ddr_command = CONFIG_SYS_MICRON_RFSH;
- im->mddrc.ddr_command = CONFIG_SYS_MICRON_NOP;
- im->mddrc.ddr_command = CONFIG_SYS_MICRON_RFSH;
- im->mddrc.ddr_command = CONFIG_SYS_MICRON_NOP;
- im->mddrc.ddr_command = CONFIG_SYS_MICRON_INIT_DEV_OP;
- im->mddrc.ddr_command = CONFIG_SYS_MICRON_NOP;
- im->mddrc.ddr_command = CONFIG_SYS_MICRON_EM2;
- im->mddrc.ddr_command = CONFIG_SYS_MICRON_NOP;
- im->mddrc.ddr_command = CONFIG_SYS_MICRON_PCHG_ALL;
- im->mddrc.ddr_command = CONFIG_SYS_MICRON_EM2;
- im->mddrc.ddr_command = CONFIG_SYS_MICRON_EM3;
- im->mddrc.ddr_command = CONFIG_SYS_MICRON_EN_DLL;
- im->mddrc.ddr_command = CONFIG_SYS_MICRON_INIT_DEV_OP;
- im->mddrc.ddr_command = CONFIG_SYS_MICRON_PCHG_ALL;
- im->mddrc.ddr_command = CONFIG_SYS_MICRON_RFSH;
- im->mddrc.ddr_command = CONFIG_SYS_MICRON_INIT_DEV_OP;
- im->mddrc.ddr_command = CONFIG_SYS_MICRON_OCD_DEFAULT;
- im->mddrc.ddr_command = CONFIG_SYS_MICRON_PCHG_ALL;
- im->mddrc.ddr_command = CONFIG_SYS_MICRON_NOP;
-
+ im->mddrc.ddr_command = CONFIG_SYS_DDR_NOP;
+
+ im->mddrc.ddr_command = CONFIG_SYS_DDR_PCHG_ALL;
+ im->mddrc.ddr_command = CONFIG_SYS_DDR_NOP;
+ im->mddrc.ddr_command = CONFIG_SYS_DDR_RFSH;
+ im->mddrc.ddr_command = CONFIG_SYS_DDR_NOP;
+ im->mddrc.ddr_command = CONFIG_SYS_DDR_RFSH;
+ im->mddrc.ddr_command = CONFIG_SYS_DDR_NOP;
+
+ if (try_elpida) {
+ /* Elpida init sequence - works for Micron too but runs slower */
+ im->mddrc.ddr_command = CONFIG_SYS_DDR_EM2;
+ im->mddrc.ddr_command = CONFIG_SYS_DDR_EM3;
+ im->mddrc.ddr_command = CONFIG_SYS_DDR_EN_DLL;
+ im->mddrc.ddr_command = CONFIG_SYS_DDR_RES_DLL;
+ im->mddrc.ddr_command = CONFIG_SYS_DDR_PCHG_ALL;
+ im->mddrc.ddr_command = CONFIG_SYS_DDR_RFSH;
+ im->mddrc.ddr_command = CONFIG_SYS_DDR_RFSH;
+ im->mddrc.ddr_command = CONFIG_SYS_DDR_RFSH;
+ im->mddrc.ddr_command = CONFIG_SYS_ELPIDA_INIT_DEV_OP;
+ udelay(200);
+ } else {
+ /* Micron init sequence */
+ im->mddrc.ddr_command = CONFIG_SYS_MICRON_INIT_DEV_OP;
+ im->mddrc.ddr_command = CONFIG_SYS_DDR_NOP;
+ im->mddrc.ddr_command = CONFIG_SYS_DDR_EM2;
+ im->mddrc.ddr_command = CONFIG_SYS_DDR_NOP;
+ im->mddrc.ddr_command = CONFIG_SYS_DDR_PCHG_ALL;
+ im->mddrc.ddr_command = CONFIG_SYS_DDR_EM2;
+ im->mddrc.ddr_command = CONFIG_SYS_DDR_EM3;
+ im->mddrc.ddr_command = CONFIG_SYS_DDR_EN_DLL;
+ im->mddrc.ddr_command = CONFIG_SYS_MICRON_INIT_DEV_OP;
+ im->mddrc.ddr_command = CONFIG_SYS_DDR_PCHG_ALL;
+ im->mddrc.ddr_command = CONFIG_SYS_DDR_RFSH;
+ im->mddrc.ddr_command = CONFIG_SYS_DDR_RFSH;
+ im->mddrc.ddr_command = CONFIG_SYS_DDR_RFSH;
+ im->mddrc.ddr_command = CONFIG_SYS_MICRON_INIT_DEV_OP;
+ udelay(200);
+ }
+ im->mddrc.ddr_command = CONFIG_SYS_DDR_OCD_DEFAULT;
+ im->mddrc.ddr_command = CONFIG_SYS_DDR_OCD_EXIT;
+ im->mddrc.ddr_command = CONFIG_SYS_DDR_NOP;
+ for (i = 0; i < 10; i++)
+ im->mddrc.ddr_command = CONFIG_SYS_DDR_NOP;
/* Start MDDRC */
im->mddrc.ddr_time_config0 = CONFIG_SYS_MDDRC_TIME_CFG0_RUN;
- im->mddrc.ddr_sys_config = CONFIG_SYS_MDDRC_SYS_CFG_RUN;
+
+ if (try_elpida)
+ im->mddrc.ddr_sys_config = CONFIG_SYS_MDDRC_SYS_CFG_ELPIDA_RUN;
+ else
+ im->mddrc.ddr_sys_config = CONFIG_SYS_MDDRC_SYS_CFG_MICRON_RUN;
+
+ if (try_elpida == 0) {
+ if (!simple_mem_check()) {
+ debug("Mem check failed\n\t");
+ try_elpida += 1;
+ im->mddrc.ddr_sys_config = CONFIG_SYS_MDDRC_SYS_CFG_EN;
+ goto retry;
+ }
+ }
+ debug("Mem check %s\n\t", simple_mem_check()? "Passes":"Fails");
return msize;
}
diff --git a/include/configs/ads5121.h b/include/configs/ads5121.h
index 8fda3f2..ab06276 100644
--- a/include/configs/ads5121.h
+++ b/include/configs/ads5121.h
@@ -130,29 +130,38 @@
* [09:05] DRAM tRP:
* [04:00] DRAM tRPA
*/
+#define CONFIG_SYS_MDDRC_SYS_CFG_RUN ~(0x10000000)
#ifdef CONFIG_ADS5121_REV2
-#define CONFIG_SYS_MDDRC_SYS_CFG 0xF8604A00
-#define CONFIG_SYS_MDDRC_SYS_CFG_RUN 0xE8604A00
-#define CONFIG_SYS_MDDRC_TIME_CFG1 0x54EC1168
-#define CONFIG_SYS_MDDRC_TIME_CFG2 0x35210864
+#define CONFIG_SYS_MDDRC_SYS_CFG_MICRON 0xF8604A00
+#define CONFIG_SYS_MDDRC_TIME_CFG1_MICRON 0x54EC1168
+#define CONFIG_SYS_MDDRC_TIME_CFG2_MICRON 0x35210864
#else
-#define CONFIG_SYS_MDDRC_SYS_CFG 0xFA804A00
-#define CONFIG_SYS_MDDRC_SYS_CFG_RUN 0xEA804A00
-#define CONFIG_SYS_MDDRC_TIME_CFG1 0x68EC1168
-#define CONFIG_SYS_MDDRC_TIME_CFG2 0x34310864
+#define CONFIG_SYS_MDDRC_SYS_CFG_MICRON 0xFA804A00
+#define CONFIG_SYS_MDDRC_SYS_CFG_MICRON_RUN 0xEA804A00
+#define CONFIG_SYS_MDDRC_TIME_CFG1_MICRON 0x68EC1168
+#define CONFIG_SYS_MDDRC_TIME_CFG2_MICRON 0x34310864
#endif
+#define CONFIG_SYS_MDDRC_SYS_CFG_ELPIDA 0xFA802b40
+#define CONFIG_SYS_MDDRC_SYS_CFG_ELPIDA_RUN 0xEA802b40
+#define CONFIG_SYS_MDDRC_TIME_CFG1_ELPIDA 0x690e1189
+#define CONFIG_SYS_MDDRC_TIME_CFG2_ELPIDA 0x35410864
+
#define CONFIG_SYS_MDDRC_SYS_CFG_EN 0xF0000000
+#define CONFIG_SYS_MDDRC_SYS_CFG_CLK_BIT (1 << 29)
+#define CONFIG_SYS_MDDRC_SYS_CFG_CKE_BIT (1 << 30)
#define CONFIG_SYS_MDDRC_TIME_CFG0 0x00003D2E
#define CONFIG_SYS_MDDRC_TIME_CFG0_RUN 0x06183D2E
-
-#define CONFIG_SYS_MICRON_NOP 0x01380000
-#define CONFIG_SYS_MICRON_PCHG_ALL 0x01100400
-#define CONFIG_SYS_MICRON_EM2 0x01020000
-#define CONFIG_SYS_MICRON_EM3 0x01030000
-#define CONFIG_SYS_MICRON_EN_DLL 0x01010000
-#define CONFIG_SYS_MICRON_RFSH 0x01080000
#define CONFIG_SYS_MICRON_INIT_DEV_OP 0x01000432
-#define CONFIG_SYS_MICRON_OCD_DEFAULT 0x01010780
+#define CONFIG_SYS_ELPIDA_INIT_DEV_OP 0x01000842
+#define CONFIG_SYS_DDR_NOP 0x01380000
+#define CONFIG_SYS_DDR_PCHG_ALL 0x01100400
+#define CONFIG_SYS_DDR_EM2 0x01020000
+#define CONFIG_SYS_DDR_EM3 0x01030000
+#define CONFIG_SYS_DDR_EN_DLL 0x01010000
+#define CONFIG_SYS_DDR_RES_DLL 0x01000932
+#define CONFIG_SYS_DDR_RFSH 0x01080000
+#define CONFIG_SYS_DDR_OCD_DEFAULT 0x01010780
+#define CONFIG_SYS_DDR_OCD_EXIT 0x01010400
/* DDR Priority Manager Configuration */
#define CONFIG_SYS_MDDRCGRP_PM_CFG1 0x00077777
--
1.5.2.4
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