On 01/12/2012 11:44, Philippe Reynes wrote:
> Signed-off-by: Philippe Reynes <trem...@yahoo.fr>
> Signed-off-by: Eric Jarrige <eric.jarr...@armadeus.org>
> Signed-off-by: Nicolas Colombain <nicolas.colomb...@armadeus.com>
> ---
> MAINTAINERS | 5 +
> board/armadeus/apf27/Makefile | 48 +++
> board/armadeus/apf27/apf27.c | 347 ++++++++++++++++++++++
> board/armadeus/apf27/apf27.h | 477 +++++++++++++++++++++++++++++++
> board/armadeus/apf27/start.S | 538
> +++++++++++++++++++++++++++++++++++
> board/armadeus/apf27/u-boot-spl.lds | 86 ++++++
> boards.cfg | 1 +
> include/configs/apf27.h | 445 +++++++++++++++++++++++++++++
> 8 files changed, 1947 insertions(+), 0 deletions(-)
> create mode 100644 board/armadeus/apf27/Makefile
> create mode 100644 board/armadeus/apf27/apf27.c
> create mode 100644 board/armadeus/apf27/apf27.h
> create mode 100644 board/armadeus/apf27/start.S
> create mode 100644 board/armadeus/apf27/u-boot-spl.lds
> create mode 100644 include/configs/apf27.h
>
Hi Philippe,
I tried your patches, but build fails:
./MAKEALL apf27
Configuring for apf27 board...
make: *** [nand_spl] Error 2
arm-linux-gnueabi-size: './u-boot': No such file
make: *** nand_spl/board/armadeus/apf27: No such file or directory. Stop.
make: *** [nand_spl] Error 2
make: *** Waiting for unfinished jobs....
Using the generic SPL, I am expecting that nand_spl is not used at all.
Objects and result should go into the SPL directory.
> +/*
> + * Fuse bank 1 row 8 is "reserved for future use" and therefore available for
> + * customer use. The APF27 board uses this fuse to store the board revision:
> + * 0: initial board revision
> + * 1: first revision - Presence of the second RAM chip on the board is blown
> in
> + * fuse bank 1 row 9 bit 0 - No hardware change
> + * N: to be defined
> + */
> +u32 get_board_rev(void)
> +{
> + struct iim_regs *iim = (struct iim_regs *)IMX_IIM_BASE;
> +
> + return readl(&iim->bank[1].fuse_regs[8]);
> +}
> +
> +/*
> + * Fuse bank 1 row 9 is "reserved for future use" and therefore available for
> + * customer use. The APF27 board revision 1 uses the bit 0 to permanently
> store
> + * the presence of the second RAM chip
> + * 0: AFP27 with 1 RAM of 64 MiB
> + * 1: AFP27 with 2 RAM chips of 64 MiB each (128MB)
> + */
> +int get_num_ram_bank(void)
This should be declared static, I think.
> +int
> +dram_init(void)
> +{
> + /* dram_init must store complete ramsize in gd->ram_size */
> + if (get_num_ram_bank() > 1) {
> + gd->ram_size = PHYS_SDRAM_2 - CONFIG_SYS_SDRAM_BASE
> + + get_ram_size((void *)PHYS_SDRAM_2, PHYS_SDRAM_2_SIZE);
> + } else {
> + gd->ram_size = get_ram_size((void *)PHYS_SDRAM_1,
> + PHYS_SDRAM_1_SIZE);
> + }
Doesn't the following code work ?
gd->ram_size = get_ram_size((void *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE) +
get_ram_size((void *)PHYS_SDRAM_2, PHYS_SDRAM_2_SIZE);
> +void dram_init_banksize(void)
> +{
> + phys_size_t ramsize = gd->ram_size;
> +
> + if (get_num_ram_bank() > 1)
> + ramsize -= PHYS_SDRAM_2 - CONFIG_SYS_SDRAM_BASE;
> +
> + gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
> + gd->bd->bi_dram[0].size = ramsize;
> + gd->ram_size = gd->bd->bi_dram[0].size;
> +
> + if (CONFIG_NR_DRAM_BANKS > 1) {
Do you need this ? It seems from your code that you can find at run time
how many banks are mounted.
> +/*
> + * Miscellaneous initialisation
> + */
> +int
> +misc_init_r(void)
> +{
> + char *s;
> + u_char * firmware_buffer = (u_char *)(CONFIG_SYS_LOAD_ADDR + \
> + CONFIG_SYS_MONITOR_LEN);
> + size_t size = 0;
> + size_t offset = -1;
> + char *autoload = getenv("firmware_autoload");
you search for the environment, but autoload is not used in this
function, right ?
> + u8 pnum;
> + struct mtd_device *dev;
> + struct part_info *part;
> +
> + /* detect compatibility issue of environment version */
> + s = getenv("env_version");
> + if ((NULL == s) || (0 != strcmp(s, CONFIG_ENV_VERSION))) {
Not clear at all. You add a version to the environment, ok, but you
check it with a version number known at compile time. Do you use it really
> + char * const vars[] = {"flash_reset_env"};
> + printf("*** Warning - Environment version change suggests: "
> + "run flash_reset_env; reset\n");
> + set_default_vars(1, vars);
> + }
> +
> + /* Unlock whole flash but U-Boot */
> + s = getenv("env_offset");
> + offset = CONFIG_ENV_OFFSET;
This seems dangerous. You can set a variable, but the offset for the
environment is defined at compile time. This does not make a lot of
sense for me.
> +void enable_caches(void)
> +{
> + /* Enable D-cache. I-cache is already enabled in start.S */
> + dcache_enable();
> +}
> +
I suggest you move this function in a separate patch to
arch/arm/cpu/arm926ejs/mx27/generic.c. This code can be used by other
boards, too.
> +++ b/board/armadeus/apf27/apf27.h
> @@ -0,0 +1,477 @@
> +#ifndef __APF27_H
> +#define __APF27_H
> +
> +/* FPGA program pin configuration */
> +#define ACFG_FPGA_PWR (GPIO_PORTF | 19) /* FPGA prog pin */
> +#define ACFG_FPGA_PRG (GPIO_PORTF | 11) /* FPGA prog pin */
> +#define ACFG_FPGA_CLK (GPIO_PORTF | 15) /* FPGA clk pin */
> +#define ACFG_FPGA_RDATA 0xD6000000 /* FPGA data addr */
> +#define ACFG_FPGA_WDATA 0xD6000000 /* FPGA data addr */
> +#define ACFG_FPGA_INIT (GPIO_PORTF | 12) /* FPGA init pin */
> +#define ACFG_FPGA_DONE (GPIO_PORTF | 9) /* FPGA done pin */
> +#define ACFG_FPGA_RW (GPIO_PORTF | 21) /* FPGA done pin */
> +#define ACFG_FPGA_CS (GPIO_PORTF | 22) /* FPGA done pin */
> +#define ACFG_FPGA_SUSPEND (GPIO_PORTF | 10) /* FPGA done pin */
> +#define ACFG_FPGA_RESET (GPIO_PORTF | 7) /* FPGA done pin */
> +
> +/* MPU CLOCK source before PLL */
> +/* ACFG_CLK_FREQ (2/3 MPLL clock or ext 266 MHZ) */
Style, wrong multiline comment.
> +#ifndef CONFIG_MX27_CLK26
> +#if (CONFIG_MX27_CLK32 == 32000)
> +#define ACFG_MPCTL0_VAL 0x00211803 /* 398.998 MHz */
> +#define ACFG_MPCTL1_VAL 0
> +#define CONFIG_MPLL_FREQ 399
> +#else /* CONFIG_MX27_CLK32 == 32768*/
> +#define ACFG_MPCTL0_VAL 0x01EF15D5 /* 399.000 MHz */
> +#define ACFG_MPCTL1_VAL 0
> +#define CONFIG_MPLL_FREQ 399
> +#endif /* CONFIG_MX27_CLK32 */
> +#else /* CONFIG_MX27_CLK26 in use*/
> +#define ACFG_MPCTL0_VAL 0x00331C23 /* 399.000 MHz */
> +#define ACFG_MPCTL1_VAL 0
> +#define CONFIG_MPLL_FREQ 399
> +#endif /* CONFIG_MX27_CLK26 */
Is it old code ? CONFIG_MX27_CLK26 is not used at all in u-boot, and you
do not define it. If we can get rid of it, please then clean up also the
other parts using #ifndef CONFIG_MX27_CLK26
> +
> +/* ARM bus frequency (have to be a CONFIG_MPLL_FREQ ratio) */
> +#define CONFIG_ARM_FREQ 399 /* up to 400 MHz */
> +
> +/* external bus frequency (have to be a ACFG_CLK_FREQ ratio) */
> +#define CONFIG_HCLK_FREQ 133 /* (ACFG_CLK_FREQ/2) */
> +
> +#define CONFIG_PERIF1_FREQ 16 /* 16.625 MHz UART, GPT, PWM*/
> +#define CONFIG_PERIF2_FREQ 33 /* 33.25 MHz CSPI and SDHC */
> +#define CONFIG_PERIF3_FREQ 33 /* 33.25 MHz LCD*/
> +#define CONFIG_PERIF4_FREQ 33 /* 33.25 MHz CSI*/
> +#define CONFIG_SSI1_FREQ 66 /* 66.50 MHz SSI1*/
> +#define CONFIG_SSI2_FREQ 66 /* 66.50 MHz SSI2*/
> +#define CONFIG_MSHC_FREQ 66 /* 66.50 MHz MSHC*/
> +#define CONFIG_H264_FREQ 66 /* 66.50 MHz H264*/
> +#define CONFIG_CLK0_DIV 3 /* Divide CLK0 by 4 */
> +#define CONFIG_CLK0_EN 1 /* CLK0 enabled */
> +
> +/* external bus frequency (have to be a CONFIG_HCLK_FREQ ratio) */
> +#define CONFIG_NFC_FREQ 44 /* NFC Clock up to 44 MHz wh
> 133MHz*/
> +
> +/* external serial bus frequency (have to be a CONFIG_SPLL_FREQ ratio) */
> +#define CONFIG_USB_FREQ 60 /* 60 MHz */
> +
> +/*
> + * SDRAM
> + */
> +#if (ACFG_SDRAM_MBYTE_SYZE == 64) /* micron MT46H16M32LF -6 */
> +/* micron 64MB */
> +#define ACFG_SDRAM_NUM_COL 9 /* 8, 9, 10 or 11
> + column address bits */
> +#define ACFG_SDRAM_NUM_ROW 13 /* 11, 12 or 13
> + row address bits */
> +#define ACFG_SDRAM_REFRESH 3 /* 0=OFF 1=2048
> + 2=4096 3=8192 refresh */
> +#define ACFG_SDRAM_EXIT_PWD 25 /* ns exit power
> + down delay */
> +#define ACFG_SDRAM_W2R_DELAY 1 /* write to read
> + cycle delay > 0 */
> +#define ACFG_SDRAM_ROW_PRECHARGE_DELAY 18 /* ns */
> +#define ACFG_SDRAM_TMRD_DELAY 2 /* Load mode register
> + cycle delay 1..4 */
> +#define ACFG_SDRAM_TWR_DELAY 1 /* LPDDR: 0=2ck 1=3ck;
> + SDRAM: 0=1ck 1=2ck*/
> +#define ACFG_SDRAM_RAS_DELAY 42 /* ns ACTIVE-to-PRECHARGE
> + delay */
> +#define ACFG_SDRAM_RRD_DELAY 12 /* ns ACTIVE-to-ACTIVE
> + delay */
> +#define ACFG_SDRAM_RCD_DELAY 18 /* ns Row to Column delay */
> +#define ACFG_SDRAM_RC_DELAY 70 /* ns Row cycle delay (tRFC
> + refresh to command) */
> +#define ACFG_SDRAM_CLOCK_CYCLE_CL_1 0 /* ns clock cycle time
> + estimated fo CL=1
> + 0=force 3 for lpddr */
> +#define ACFG_SDRAM_PARTIAL_ARRAY_SR 0 /* 0=full 1=half 2=quater
> + 3=Eighth 4=Sixteenth */
> +#define ACFG_SDRAM_DRIVE_STRENGH 0 /* 0=Full-strength 1=half
> + 2=quater 3=Eighth */
> +#define ACFG_SDRAM_BURST_LENGTH 3 /* 2^N BYTES (N=0..3) */
> +#define ACFG_SDRAM_SINGLE_ACCESS 0 /* 1= single access;
> + 0 = Burst mode */
> +#endif
> +
> +#if (ACFG_SDRAM_MBYTE_SYZE == 128)
> +/* micron 128MB */
> +#define ACFG_SDRAM_NUM_COL 9 /* 8, 9, 10 or 11
> + column address bits */
> +#define ACFG_SDRAM_NUM_ROW 14 /* 11, 12 or 13
> + row address bits */
> +#define ACFG_SDRAM_REFRESH 3 /* 0=OFF 1=2048
> + 2=4096 3=8192 refresh */
> +#define ACFG_SDRAM_EXIT_PWD 25 /* ns exit power
> + down delay */
> +#define ACFG_SDRAM_W2R_DELAY 1 /* write to read
> + cycle delay > 0 */
> +#define ACFG_SDRAM_ROW_PRECHARGE_DELAY 18 /* ns */
> +#define ACFG_SDRAM_TMRD_DELAY 2 /* Load mode register
> + cycle delay 1..4 */
> +#define ACFG_SDRAM_TWR_DELAY 1 /* LPDDR: 0=2ck 1=3ck;
> + SDRAM: 0=1ck 1=2ck*/
> +#define ACFG_SDRAM_RAS_DELAY 42 /* ns ACTIVE-to-PRECHARGE
> + delay */
> +#define ACFG_SDRAM_RRD_DELAY 12 /* ns ACTIVE-to-ACTIVE
> + delay */
> +#define ACFG_SDRAM_RCD_DELAY 18 /* ns Row to Column delay */
> +#define ACFG_SDRAM_RC_DELAY 70 /* ns Row cycle delay (tRFC
> + refresh to command)*/
> +#define ACFG_SDRAM_CLOCK_CYCLE_CL_1 0 /* ns clock cycle time
> + estimated fo CL=1
> + 0=force 3 for lpddr*/
> +#define ACFG_SDRAM_PARTIAL_ARRAY_SR 0 /* 0=full 1=half 2=quater
> + 3=Eighth 4=Sixteenth */
> +#define ACFG_SDRAM_DRIVE_STRENGH 0 /* 0=Full-strength 1=half
> + 2=quater 3=Eighth */
> +#define ACFG_SDRAM_BURST_LENGTH 3 /* 2^N BYTES (N=0..3) */
> +#define ACFG_SDRAM_SINGLE_ACCESS 0 /* 1= single access;
> + 0 = Burst mode */
> +#endif
> +
> +#if (ACFG_SDRAM_MBYTE_SYZE == 256)
> +/* micron 256MB */
> +#define ACFG_SDRAM_NUM_COL 10 /* 8, 9, 10 or 11
> + column address bits */
> +#define ACFG_SDRAM_NUM_ROW 14 /* 11, 12 or 13
> + row address bits */
> +#define ACFG_SDRAM_REFRESH 3 /* 0=OFF 1=2048
> + 2=4096 3=8192 refresh */
> +#define ACFG_SDRAM_EXIT_PWD 25 /* ns exit power
> + down delay */
> +#define ACFG_SDRAM_W2R_DELAY 1 /* write to read cycle
> + delay > 0 */
> +#define ACFG_SDRAM_ROW_PRECHARGE_DELAY 18 /* ns */
> +#define ACFG_SDRAM_TMRD_DELAY 2 /* Load mode register
> + cycle delay 1..4 */
> +#define ACFG_SDRAM_TWR_DELAY 1 /* LPDDR: 0=2ck 1=3ck;
> + SDRAM: 0=1ck 1=2ck */
> +#define ACFG_SDRAM_RAS_DELAY 42 /* ns ACTIVE-to-PRECHARGE
> + delay */
> +#define ACFG_SDRAM_RRD_DELAY 12 /* ns ACTIVE-to-ACTIVE
> + delay */
> +#define ACFG_SDRAM_RCD_DELAY 18 /* ns Row to Column delay */
> +#define ACFG_SDRAM_RC_DELAY 70 /* ns Row cycle delay (tRFC
> + refresh to command) */
> +#define ACFG_SDRAM_CLOCK_CYCLE_CL_1 0 /* ns clock cycle time
> + estimated fo CL=1
> + 0=force 3 for lpddr */
> +#define ACFG_SDRAM_PARTIAL_ARRAY_SR 0 /* 0=full 1=half 2=quater
> + 3=Eighth 4=Sixteenth */
> +#define ACFG_SDRAM_DRIVE_STRENGH 0 /* 0=Full-strength
> + 1=half
> + 2=quater
> + 3=Eighth */
> +#define ACFG_SDRAM_BURST_LENGTH 3 /* 2^N BYTES (N=0..3) */
> +#define ACFG_SDRAM_SINGLE_ACCESS 0 /* 1= single access;
> + 0 = Burst mode */
> +#endif
I understand why, but maybe it is more readable if you define a table in
apf27.c and you access to it on depend of the selected RAM. Something like:
struct ram_timing {
.....
}
struct ram_timing apf27_ram[] = {
{... }, /* 64 MB */
{...}, /* 128 MB */
{...} /* 256 MB */
}
What do you think about ?
> +/*
> + * Default configuration for GPIOs and peripherals
> + */
> +#ifndef ACFG_APF27_CUSTOM
> +#define ACFG_DDIR_A_VAL 0x00000000
> +#define ACFG_OCR1_A_VAL 0x00000000
> +#define ACFG_OCR2_A_VAL 0x00000000
> +#define ACFG_ICFA1_A_VAL 0xFFFFFFFF
> +#define ACFG_ICFA2_A_VAL 0xFFFFFFFF
> +#define ACFG_ICFB1_A_VAL 0xFFFFFFFF
> +#define ACFG_ICFB2_A_VAL 0xFFFFFFFF
> +#define ACFG_DR_A_VAL 0x00000000
> +#define ACFG_GIUS_A_VAL 0xFFFFFFFF
> +#define ACFG_ICR1_A_VAL 0x00000000
> +#define ACFG_ICR2_A_VAL 0x00000000
> +#define ACFG_IMR_A_VAL 0x00000000
> +#define ACFG_GPR_A_VAL 0x00000000
> +#define ACFG_PUEN_A_VAL 0xFFFFFFFF
I am unsure if I have understood. This seems the setup of the GPIOs
controller, and for that we have gpio_ function. Why do we need all this
stuff ?
> +/* Enforce DDR signal strengh & enable USB/PP/DMA burst override bits */
> +#define ACFG_GPCR_VAL 0x0003000F
> +
> +#define ACFG_ESDMISC_VAL ESDMISC_LHD+ESDMISC_MDDREN
> +
> +/* FMCR select num LPDDR RAMs and nand 16bits, 2KB pages */
> +#if (CONFIG_NR_DRAM_BANKS == 1)
> +#define ACFG_FMCR_VAL 0xFFFFFFF9
> +#elif (CONFIG_NR_DRAM_BANKS == 2)
> +#define ACFG_FMCR_VAL 0xFFFFFFFB
> +#endif
> +
> +#ifndef ACFG_APF27_CUSTOM
..but ACFG_APF27_CUSTOM is not set at all - also old code and can we
clean up ?
> diff --git a/board/armadeus/apf27/start.S b/board/armadeus/apf27/start.S
> new file mode 100644
> index 0000000..05d5de0
> --- /dev/null
> +++ b/board/armadeus/apf27/start.S
> @@ -0,0 +1,538 @@
> +/*
> + * IMX27 NAND Flash SPL (Secondary Program Loader)
> + *
> + * Copyright (c) 2008 Armadeus Project / eja
> + *
> + * Based on Freescale NAND SPL
> + *
> + * Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
> + * Copyright (c) 2008-2012 Eric Jarrige <eric.jarr...@armadeus.org>
> + *
> + * See file CREDITS for list of people who contributed to this
> + * project.
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of
> + * the License, or (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
> + * MA 02111-1307 USA
> + */
> +
> +
> +#include <config.h>
> +#include <generated/asm-offsets.h>
> +#include <version.h>
> +#include <asm/macro.h>
> +#include <asm/arch/mxc_nand.h>
> +#include <asm/arch/imx-regs.h>
> +#include "apf27.h"
> +
> +/*
> + * Standard NAND flash commands
> + */
> +#define NAND_CMD_READ0 0
> +#define NAND_CMD_READ1 1
> +#define NAND_CMD_PAGEPROG 0x10
> +#define NAND_CMD_READOOB 0x50
> +#define NAND_CMD_ERASE1 0x60
> +#define NAND_CMD_STATUS 0x70
> +#define NAND_CMD_STATUS_MULTI 0x71
> +#define NAND_CMD_SEQIN 0x80
> +#define NAND_CMD_READID 0x90
> +#define NAND_CMD_ERASE2 0xd0
> +#define NAND_CMD_RESET 0xff
> +
> +/* Extended commands for large page devices */
> +#define NAND_CMD_READSTART 0x30
> +#define NAND_CMD_CACHEDPROG 0x15
> +
> +/* Status bits */
> +#define NAND_STATUS_FAIL 0x01
> +#define NAND_STATUS_FAIL_N1 0x02
> +#define NAND_STATUS_TRUE_READY 0x20
> +#define NAND_STATUS_READY 0x40
> +#define NAND_STATUS_WP 0x80
> +
> + .macro nand_boot
> +
> +#ifdef CONFIG_BOOT_TRACE_REG
> +/*
> + * If CONFIG_BOOT_TRACE_REG is a SDRAM address then be sure to use the
> following
> + * 2 command after SDRAM init
> + */
> +
> +/* Backup state of previous boot to CONFIG_BOOT_TRACE_REG+4*/
> +#define BACKUP_TRACE() \
> + ldr r4, =CONFIG_BOOT_TRACE_REG; \
> + ldr r3, [r4]; \
> + str r3, [r4, #0x04];
> +
> +/* Save a state of boot at CONFIG_BOOT_TRACE_REG */
> +#define BOOT_TRACE(val) \
> + ldr r4, =CONFIG_BOOT_TRACE_REG; \
> + ldr r3, =val; \
> + str r3, [r4];
> +#else
> +#define BACKUP_TRACE()
> +#define BOOT_TRACE(val)
> +#endif
> +
> +nand_boot_setup:
> +
> + /* Copy SPL image from flash to SDRAM first */
> + BOOT_TRACE(1)
> + ldr r0, =IMX_NFC_MAIN_AREA0
> + add r2, r0, #(IMX_NFC_SPARE_AREA0-IMX_NFC_MAIN_AREA0) //2KB NFC Buff
> + ldr r1, =CONFIG_SYS_NAND_U_BOOT_DST
> +
> + BOOT_TRACE(2)
> +1: ldmia r0!, {r3-r10}
> + stmia r1!, {r3-r10}
> + cmp r0, r2
> + blo 1b
> +
If SPL can link mxc_nand.c, you have all functions if you link also
nand_spl_simple.o and nand_spl_load.o. Why do we need to redefine them
in assembly ?
> +
> +
> + /* Jump to SDRAM */
> + BOOT_TRACE(3)
> + ldr r1, =0x7FF
> + and r0, pc, r1 /* offset of pc */
> + ldr r1, =CONFIG_SYS_NAND_U_BOOT_DST
> + add r1, r1, #0x10
> + add pc, r0, r1
This is also done by generic SPL code.
> +.globl _start
> +_start:
> +
> +/*
> + *************************************************************************
> + *
> + * Startup Code (reset vector)
> + *
> + * do important init only if we don't start from memory!
> + * setup Memory and board specific bits prior to relocation.
> + * relocate armboot to ram
> + * setup stack
> + *
> + *************************************************************************
> + */
> +
> +
> +/*
> + * the actual reset code
> + */
> +
> +reset:
> + /*
> + * set the cpu to SVC32 mode
> + */
> + mrs r0,cpsr
> + bic r0,r0,#0x1f
> + orr r0,r0,#0xd3
> + msr cpsr,r0
> +
> + /*
> + * invalidate I/D cache/TLB and drain write buffer
> + */
> + mov r0, #0
> + mcr p15, 0, r0, c7, c7, 0 /* invalidate I cache and D cache */
> + mcr p15, 0, r0, c8, c7, 0 /* invalidate TLBs */
> + mcr p15, 0, r0, c7, c10, 4 /* Drain the write buffer */
> +
> + /*
> + * disable MMU stuff and caches
> + */
> + mrc p15, 0, r0, c1, c0, 0
> + bic r0, r0, #0x00002300 /* clear bits 13, 9:8 (--V- --RS) */
> + bic r0, r0, #0x00000087 /* clear bits 7, 2:0 (B--- -CAM) */
> + orr r0, r0, #0x00000002 /* set bit 2 (A) Align */
> + orr r0, r0, #0x00001000 /* set bit 12 (I) I-Cache */
> + mcr p15, 0, r0, c1, c0, 0
> +
You also duplicate stuff that is in the generic
arch/arm/cpu/arm926ejs/start.S. Better, you substitute the generic one
with yours. But the generic has support to call SPL function, so why to
replace it ?
> +/*
> + * SPL
> + */
> +/* Copy SPL+U-Boot here */
> +#define CONFIG_SYS_NAND_U_BOOT_DST (CONFIG_SYS_TEXT_BASE - 0x800)
> +/* Size is the partion size */
> +#define CONFIG_SYS_NAND_U_BOOT_SIZE CONFIG_SYS_MONITOR_LEN
> +/* Build image with spl and u-boot */
> +#define CONFIG_NAND_U_BOOT
> +#define CONFIG_SPL_PAD_TO 0xa1000000
> +
> +/*
> + * SPL
> + */
> +#define CONFIG_SPL
> +#define CONFIG_SPL_NO_CPU_SUPPORT_CODE
I have not understood why using CONFIG_SPL_FRAMEWORK does not work for
you. You should have availbale a lot of function that you redefine in
your patches.
Best regards,
Stefano Babic
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DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sba...@denx.de
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